Job Requirements
The SOC DV Lead focuses on the "big picture." This role is responsible for ensuring that all integrated components (IPs) communicate correctly, the memory map is accurate, and the system-level use cases—like boot-up and power management—function seamlessly.
Core Responsibilities
Testplan Ownership: Define and execute the top-level SOC verification plan, focusing on chip-level connectivity, pinmuxing, and system-level scenarios.
Infrastructure Architecture: Architect scalable SOC-level testbenches using UVM and C-based verification environments.
Subsystem Integration: Oversee the integration of third-party and in-house IPs into the SOC environment.
Performance & Power: Verify system-level performance bottlenecks and power-aware (UPF) sequences.
Gate-Level Simulation: Lead the strategy for GLS and oversee timing-critical verification.
Mentorship: Guide a team of engineers, manage schedules, and interface with Architecture and Physical Design teams.
Required Skills & Qualifications
Experience: 10+ years in ASIC/SOC verification.
Technical Mastery: Expert knowledge of SystemVerilog/UVM and C/C++ for embedded firmware verification.
Protocols: Deep understanding of bus protocols like AMBA (AXI, ACE, CHI) and high-speed interfaces (PCIe, DDR).
System Knowledge: Proven track record with multi-clock domains (CDC), reset sequences, and interrupt controllers.
Tools: Mastery of industry-standard simulators (VCS/Xcelium) and hardware emulators (Palladium/Zebu).
