Senior RTL Design / SoC Integration Engineer
Senior RTL Design / SoC Integration Engineer with 8+ years of experience in ASIC/SoC design and integration. The role involves authoring and owning third-party IP integration, performing multi-domain CDC analysis, and developing ASEP 8-port interfaces including 32-to-16-bit width adaptation, asynchronous FIFO design, stype routing, and SOP/EOP framing. The engineer will be responsible for APB/SoC slave bus bridge development, register map ownership, and implementation using RGGEN-based CSR methodology.
The ideal candidate should possess strong expertise in SystemVerilog RTL design and assertions, along with hands-on experience in lint analysis and closure using Cadence HAL and SpyGlass tools. Experience with Cadence CDC tools for clock domain crossing verification and sign-off is required. A solid understanding of ASA-ML DLL, PCS, OAM, PTB, and ASEP protocol layers is essential, along with the ability to interpret and work from PHY specifications and datasheets.
The role also requires implementing Functional Safety (FuSa) mechanisms including MBIST, LBIST, redundancy architectures, and fault-detection techniques to ensure the chip complies with ISO 26262 safety requirements. The engineer will collaborate closely with architecture, verification, DFT, and system teams to deliver high-quality, production-ready silicon solutions.
Pay: Up to ₹4,000,000.00 per year
Experience:
- RTL Design : 8 years (Required)
Work Location: In person
