Hiring: STA Engineer
Location: Bangalore
Experience: 4+ Years
Job Summary:
We are looking for a skilled STA Engineer with experience in ASIC design flow and timing signoff activities. The candidate should have strong expertise in Static Timing Analysis, timing closure, and SDC constraint development.
Key Responsibilities:
- Perform block-level and full-chip Static Timing Analysis (STA)
- Develop and validate SDC constraints
- Execute MMMC timing analysis and timing signoff
- Debug and resolve setup and hold violations
- Analyze clock skew, jitter, and signal integrity effects
- Drive timing closure across various stages of the design flow
- Generate and implement timing ECOs
- Collaborate with RTL, Physical Design, and Signoff teams
Required Skills:
- Strong understanding of ASIC Design Flow (RTL-to-GDS)
- Hands-on experience with Tempus STA Tool
- Expertise in timing closure methodologies
- Knowledge of MMMC analysis
- Experience with setup/hold debugging
- Understanding of signal integrity concepts
- Experience with clock tree analysis, skew, and jitter
- Ability to create timing ECOs
Preferred Qualifications:
- Bachelor's or Master's degree in Electronics, ECE, VLSI, or related field
- Good communication and problem-solving skills
Contact:
Prem Kumar – 7418256381
Interested candidates can share their updated resume or contact for more details.
Pay: ₹323,103.91 - ₹1,417,611.64 per year
Benefits:
- Paid sick time
- Provident Fund
Work Location: In person
