Role description
FPGA Design Sr. Engineer
- FPGA Design Engineer: 5-7+ years experience in Intel/Altera FPGAs (Agilex, Stratix 10, Arria 10)
- Strong in RTL development using Verilog/SystemVerilog.
- Skilled in Quartus Prime Pro, Platform Designer, timing constraints, and achieving block level timing closure
Supports FPGA Lead with architecture reviews, subsystem planning, performance tuning, and system integration activities.
Skills
vlsi design,fpga design,altera fpgas,verilog,
About UST
UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients’ organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact—touching billions of lives in the process.
