Role description
FPGA RTL Design Engineer
- Strong Verilog/SystemVerilog design expertise
- Experience building PCIe DMA datapaths, packet generators/checkers, and memory mapped subsystems
- Familiarity with Avalon ST/Avalon MM/AXI protocols
- Implementing register maps, control logic, FIFOs, error injection blocks
- Writing synthesizable, lint clean RTL and module-level testbenches
Skills
vlsi design,verilog,pcie,fifos,rtl design,
About UST
UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients’ organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact—touching billions of lives in the process.
