Required Skills
5+ years of RTL Design experience.Strong expertise in Micro-Architecture and RTL Design.Proficiency in Verilog/SystemVerilog.Good understanding of ASIC/SoC design flow.Experience with synthesis and linting tools.Knowledge of AMBA protocols (AXI/AHB/APB) is preferred.Strong debugging and problem-solving skills.Key
Responsibilities
Develop Micro-Architecture specifications from system and architecture requirements.Design and implement RTL using Verilog/SystemVerilog.Perform design reviews and ensure coding best practices.Collaborate with Verification, DFT, Physical Design, and STA teams.Support synthesis, timing closure, and design sign-off activities.Debug and resolve functional and integration issues.Participate in SoC-level design integration activities.
Location & Work Model Bangalore, India
Onsite – 5 Days per Week (No Remote Work)
Pay: ₹100,000.00 - ₹210,000.00 per month
Work Location: In person
