Job Requirements
Role: Trainee Engineer
Ensure chip design works correctly before fabrication (no bugs, meets requirements).
Key Responsibilities
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Create test plans and test cases for design validation [vlsifirst.com]
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Develop testbenches (SystemVerilog/UVM) to simulate design behavior [velvetjobs.com]
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Run simulations and debug issues in RTL/design [semivlsi.com]
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Analyze coverage to ensure all scenarios are tested [semivlsi.com]
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Identify and fix functional bugs before tape-out [maven-silicon.com]
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Work closely with design/RTL engineers and architects [careers.ti.com]
Basic Skills
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SystemVerilog / UVM
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Digital design fundamentals
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Debugging & problem solving
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Knowledge of protocols (AXI, APB, etc.)
Work Experience
- SystemVerilog / UVM
-
Digital design fundamentals
-
Debugging & problem solving
-
Knowledge of protocols (AXI, APB, etc.)
