Designation / Position: Senior Analog/RF Mixed-Signal Design Engineer
Job Description: We are seeking an experienced Senior Analog/RF Mixed-Signal Design Engineer to lead the design and development of high-performance Analog, RF, and Mixed-Signal circuits for advanced semiconductor products. The ideal candidate will have strong expertise in analog circuit design, RF building blocks, transistor-level design, and silicon validation, with the ability to drive projects from architecture through silicon bring-up while mentoring junior engineers.
Desired Skills/Experience:
B.E./B.Tech, M.E./M.Tech, or Ph.D. in Electronics, Electrical Engineering, Microelectronics, VLSI, or a related field.
05–08 years of experience in Analog/RF Mixed-Signal IC Design.
Strong expertise in Analog design (LDO, BGR, Op-Amps, Comparators, Bias Circuits, PMIC).
Hands-on experience with RF building blocks (PLL, Fractional-N PLL, VCO, Frequency Synthesizer, Charge Pump, PFD, Mixers, RF Transceiver, RX/TX Front-End).
Proficiency in Cadence Virtuoso/Spectre, transistor-level design, simulation, and post-layout verification.
Experience with silicon bring-up, debugging, and cross-functional collaboration.
Qualification-
Minimum
UG:B.Tech/B.E. in Electronics/Electronics &Telecommunication
Desirable
PG:M.Tech in Electronics/Electronics &Telecommunication, VLSI.
PhD: (Electronics/Electronics &Telecommunication)
Roles and Responsibilities:
Lead the design and development of Analog, RF, and Mixed-Signal IPs for advanced IC/SoC products.
Architect, design, and optimize analog building blocks including LDO, Bandgap Reference (BGR), Bias Generators, Current Mirrors, Operational Amplifiers, Comparators, Voltage References, Analog Bias Networks, and PMIC circuits.
Design and integrate RF blocks such as PLL, Fractional-N PLL, Frequency Synthesizers, VCO, Charge Pump, PFD, Frequency Divider, LO Generation, RF Clock Distribution, RF Transceivers, RX/TX Front-End, Mixers, and IF Circuits.
Drive transistor-level design, simulation, post-layout verification, silicon bring-up, and performance optimization.
Provide technical leadership, mentor junior engineers, and collaborate with cross-functional teams to deliver high-quality silicon.
Work Location: In person
