Project Lead - FPGA

Logic-fruit Technologies -
Bengaluru, Karnataka

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Job details

Qualifications

Oracle
FPGA
Verilog
Embedded software
Ethernet
Project leadership
Debugging

Full job description

Project Lead - FPGA

As FPGA Design Lead, your role will be to manage and lead design engineers to implement complex FPGA IPs and FPGA-based digital designs. You should be able to understanding the project requirements and define architecture/Micro architecture with proper documentation. You will be guiding the team for system development, verification, and/or debugging and HW/SW integration.

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Home / About Us / Career / Current Openings / FPGA Project Lead

Job Position : Project Lead (FPGA)

Experience : 6+ Years

Location : Gurugram/Bengaluru

Responsibilities :

You will develop RTL code to implement FPGA-based digital designs , working from specification stage through to system integration. Projects will range from Mid to multi-million gates. Most projects include designing logic for latest generation of high speed serial protocols like PCIe gen5, Gen6, USB 3.2 Ethernet 10G/25G/100G, digital signal processing and control logic (bus interfaces and state machines)
Understand the customer requirements and product definition
Define architecture and detailed design spec based on requirements and various trade-offs
Micro-architecture and coding of assigned module in VHDL/Verilog
Write test bench for verifying design for complete scenario coverage
Implementation of the design for porting on FPGA after required optimization based on available resources and timing closure requirement
FPGA debugging and HW/SW integration

Requirements:

6+ years of experience, including successful completion of FPGA based projects
Coding experience in VHDL and/or Verilog is must
Experience targeting Xilinx and/or Altera FPGAs required
Familiarity with tools like Modelsim, Questasim, Xilinx Vivado, Planahead, Altera Quartus etc. is required
Familiarity with debugging tools like Chipscope, Signal Tap, Logic analyzer, Scope, FPGA editor
Implementation of designs with multiple clock domains is required
Thorough understanding of appropriate coding styles for FPGAs, and trade-offs for density and speed
Experience in RTL implementation of DSP algorithms will be appreciated
Experience in development of PCIe, USB, Ethernet transceivers, DDRx, ADC, DAC, AMBA-AXI, SRAM, USB, UART, I2C, SPI will be appreciated

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Project Lead - FPGA

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