Qualcomm India Private Limited
Engineering Group, Engineering Group > Hardware Engineering
General Summary:
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.
Minimum Qualifications:
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
Experienced DDR-PHY Design Verification engineer to work on next generation System-on-chip (SoC) for smartphones, tablets, laptops.
Job responsibilities:
12 to 15 years of experience in Design Verification of complex IPs. Hands-on experience and very good understanding of DDRPHY architecture, DFI protocol and Jedec standards for latest Gens.
Ownership of DV test bench and other associated collaterals (Checkers, Scoreboards, Assertion, Functional Coverage).
Develop test plan and test cases to cover design feature set, follow up with stake holders at different levels of test bench.
Work closely with Design, Subsystem/SOC, SVE teams on failure debugs, code/functional coverage closure, as well as DSF.
Debug of regression signatures and identifying bug fixes.
Responsible for Quality sign-off and required documentation.
Debug and root cause SS/SOC/post silicon issues in collaboration with Design teams.
Expertise in IP level /Sub-system level verification.
Understanding of standard bus protocol like AHB, AXI protocols would be a plus.
Required skillset:
Experience in verification and general computational logic design/verification concepts.
Expertise in Verilog/System Verilog and UVM/OVM.
Functional Verification, Coverage, Gate Simulation (GLS), Low Power Verification, Formal Verification
Strong debugging, Analytical and problem-solving skills.
Experience in developing Monitors, Scoreboards, Sequencers that utilize System Verilog, and UVM methodologies for complex scenario generation and verification of DUT.
Experience in Scripting languages like Perl /Tcl would be a plus.
Post-si bring-up and HW-SW debug experience would be a plus.
Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [email protected] or call Qualcomm's toll-free number found here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
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If you would like more information about this role, please contact Qualcomm Careers .
