Engineer ran Jobs

Lead Engineer Embedded Linux BSP
GreenWave Radios™ —Bengaluru, Karnataka
- Oracle
- Master's degree
- C++
Quick apply
AI Product Operations & Solutions (Associate | Senior Associate | Lead)
Blue Machines AI —Bengaluru, Karnataka
- English
- Accounting
- APIs
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TAC Engineer - Fixed Wireless
Cambium Networks —Bengaluru, Karnataka
- Full-time
- Hybrid work
- Computer Science
- PMP
- Customer service
Member of Technical Staff - Sys
Aptiv plc —Chennai, Tamil Nadu
- Full-time
- DevOps
- Microsoft Office
- Analysis skills
Experienced Engineer - ASIC Design
Ericsson —Chennai, Tamil Nadu
- English
- Electrical experience
- Bachelor's degree
2d
Lead Engineer - ASIC Verification
Ericsson —Bengaluru, Karnataka
- English
- Electrical experience
- Bachelor's degree
RIC RAN Developer /Telecom Systems
SFJ Business solutions —Bengaluru, Karnataka
- ₹33 - ₹35 a year
- Full-time
- Software troubleshooting
- C++
- Communication skills
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Manager - Quality
Vodafone Idea —Surat, Gujarat
- Management
- Analysis skills
- Computer networking
Lead Engineer - ASIC Design
Ericsson —Bengaluru, Karnataka
- English
- Electrical experience
- Bachelor's degree
Senior Engineer - ASIC Design
Ericsson —Chennai, Tamil Nadu
- English
- Electrical experience
- Bachelor's degree
1d
Manager- Quality
Vodafone Idea —Ahmedabad, Gujarat
- Management
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Quantitative Investment Strategies, Vice President, Institutional Equity Division
Morgan Stanley —Mumbai, Maharashtra
- Full-time
- Java
- Master's degree
- C++
AI Architect with Telecommunications (Telco /OSS)
CGI —Chennai, Tamil Nadu
- Full-time
- Azure
- DevOps
- Master's degree
Quick apply
Gen AI Engineer with Telecommunications (Telco - OSS)
CGI —Chennai, Tamil Nadu
- Full-time
- Azure
- DevOps
- Master's degree
Quick apply
Senior Member of Technical Staff - Sys
Aptiv plc —Chennai, Tamil Nadu
- DevOps
- AWS
- AI
C++ / Java Developer
GVMS Infotech —Hyderabad, Telangana
- Java
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MSET QR Data Strats , Senior Manager , Institutional Equity Division
Morgan Stanley —Mumbai, Maharashtra
- Full-time
- Computer Science
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11d
Head Barista
Sourdough Sophia —Forbesganj, Bihar
- ₹14.00 - ₹14.50 an hour
- Email
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- Cooking
- Flexible schedule
- Food provided
Team Leader
Sourdough Sophia —Forbesganj, Bihar
- ₹14.00 - ₹14.50 an hour
- Email
- Hospitality
- Customer service
- Cooking
- Flexible schedule
- Food provided
MBSS Engineer (Security Compliance Associate)
NOKIA —India
- Full-time
- Azure
- Computer Science
- Bachelor's degree

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Lead Engineer Embedded Linux BSP

GreenWave Radios™
Bengaluru, Karnataka

Quick apply

Job details

Qualifications

Oracle
FPGA
R
Build automation
Master's degree
Bash (Unix shell)
OS Kernels
C++
C
Bachelor's degree
Embedded software
B.E.
Linux
ARM
Electrical Engineering
Python
Debugging

Full job description

InnoPhase Inc., DBA GreenWave Radios™, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays.

Headquartered in San Diego, California, GreenWave Radios™ has established itself as a pioneer in delivering power-efficient digital-to-RF solutions. The company is supported by a talented team of over 100 engineers spread across four global R&D facilities. With an extensive portfolio of more than 120 global patents, GreenWave Radios™ continues to push the boundaries of radio technology and innovation.

To learn more about GreenWave Radios™ and hear what our employees have to say, visit the GreenWave™ certification profile at GreatPlacetoWork.com or explore our Home - GreenWave Radios website.

InnoPhase Inc., DBA GreenWave™ Radios and Synergic Emergence have a co-employment relationship. For over three years, GreenWave Radios has partnered with Synergic Emergence, a professional employment organization provider, to offer our employees the best benefits and services. This arrangement means that Synergic Emergence provides employee pay checks and benefits, and GreenWave Radios will provide employment, evaluation, and advancement. By outsourcing some HR functions, GreenWave Radios can focus on what we do best – developing and implementing highly innovative SOC cellular radio integrated circuit products.

This is a BSP-focused leadership role for an engineer who brings deep expertise in board bring-up, Linux kernel, and platform software on ARM-based SoCs . The role centres on owning the software platform layer for O-RU products built on Xilinx MPSoC, RFSoC, or equivalent SoCs. FPGA experience is welcome and advantageous, but the core mandate is delivering a robust, production-grade BSP and embedded Linux stack that enables the full O-RU signal chain and O-RAN management plane. You will lead a team of BSP and embedded software engineers, define the platform software architecture, and collaborate closely with hardware, RF, PHY, and FPGA teams to bring O-RU platforms from silicon to production.

Key Responsibilities

Own end-to-end BSP development for O-RU platforms based on Xilinx ZU+ MPSoC / RFSoC or other ARM Cortex-A/R SoCs.
Lead hardware bring-up from bare board to functional system: power sequencing, clocking, DDR training, peripheral initialization.
Develop and maintain FSBL (First Stage Bootloader), PMU/PLM firmware, ARM Trusted Firmware (TF-A), and U-Boot for Zynq UltraScale+ and Versal platforms.
Author and maintain device tree sources (DTS) for all platform peripherals: RF Data Converter tiles, DMA engines, Ethernet MACs, UART, I2C, SPI, GPIO.
Develop production-grade Linux BSP using PetaLinux / Yocto with custom meta-layers for O-RU hardware.
Collaborate with hardware team on schematic reviews, signal integrity, and component selection for SoC peripherals.
Port, customize, and maintain Linux kernel for target SoC platform aligned with LTS releases (5.15, 6.1, 6.6).
Develop Linux kernel drivers for platform-specific peripherals: Xilinx RFDC (RF Data Converter), AXI DMA / MCDMA, high-speed Ethernet (10G/25G), PTP hardware clock.
Debug kernel panics, memory corruption, latency spikes, and boot failures using JTAG, GDB, ftrace, perf, and crash analysis.
Profile and optimize BSP-level latency to meet O-RAN T2a / Ta3 timing requirements from fronthaul interface to RF chain.
Develop and maintain IEEE 1588v2 PTP (G.8275.1 Telecom Profile) and SyncE software stack for O-RAN S-Plane timing compliance.
Build and maintain Yocto-based Linux distro with BSP layer, security hardening (dm-verity, secure boot, TrustZone), and OTA update support via SWUpdate.
Integrate Xilinx PL (Programmable Logic) IP blocks — eCPRI framer, IQ DMA, beamforming control — with PS-side Linux drivers via AXI4-Lite and AXI4- Stream.
Represent BSP platform in cross-functional reviews with RF, PHY, O-RAN stack, and product teams.

Job requirements

8+ years of core BSP & Embedded Linux Experience with B.E. / B.Tech or M.Tech in Electronics & Communication, Electrical Engineering, or Computer Engineering.
Deep expertise in BSP development for ARM Cortex-A/R SoCs.
Hands-on Linux kernel internals: memory management, DMA subsystem, interrupt handling, device tree, clock framework, power management (PM / PSCI).
Strong C programming skills for kernel and embedded firmware development.
Scripting: Python, Bash, Tcl for build automation, test scripting, and hardware bring-up utilities.
Hardware debug skills: JTAG (Lauterbach, Xilinx HS3 / HS2), oscilloscope, logic analyser, serial console bring-up.
Familiarity with O-RAN Alliance O-RU architecture and WG4 fronthaul split (eCPRI, CUS-Plane, M-Plane, S-Plane).
C++ experience for developing BSP-level user-space services, configuration daemons, or test harnesses.

Benefits:

Competitive salary and stock options.
Learning and development opportunities.
Employer-paid health Insurance.
Earned, Casual, Sick & parental leaves.

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Refine Your Search

Lead Engineer Embedded Linux BSP

AI Product Operations & Solutions (Associate | Senior Associate | Lead)

TAC Engineer - Fixed Wireless

Member of Technical Staff - Sys

Experienced Engineer - ASIC Design

Lead Engineer - ASIC Verification

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Manager - Quality

Lead Engineer - ASIC Design

Senior Engineer - ASIC Design

Manager- Quality

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Gen AI Engineer with Telecommunications (Telco - OSS)

Senior Member of Technical Staff - Sys

C++ / Java Developer

MSET QR Data Strats , Senior Manager , Institutional Equity Division

Head Barista

Team Leader

MBSS Engineer (Security Compliance Associate)

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