Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You have built a career in physical design where the difference between a chip that tapes out on schedule and one that misses by three months often comes down to decisions you made during floorplanning or a routing strategy you adjusted at 3nm. You know that backend implementation is not just about running tools, it is about understanding when to push timing closure harder and when to step back and rethink your approach entirely.
You have seen enough tapeouts to know that customer success is not about showing what a tool can do in a perfect testcase. It is about sitting with an engineer who is stuck at 87% timing closure on a real design with real constraints and helping them find the path through. You ask the right questions before you start optimizing. You listen to what is actually blocking progress, not what the ticket says.
Working directly with customers energizes you because every engagement is different. One week you are debugging a CTS issue at an advanced node, the next you are walking a team through AI-driven placement strategies they have never tried. You do not need a script. You need the problem, the data, and enough context to move.
At Synopsys, you will work with customers who are building the chips that matter, and the solutions you help them implement will directly affect their ability to ship.
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Support customer engagements across the full ASIC design flow, from RTL to GDSII, with a focus on physical implementation using Synopsys backend tools including Fusion Compiler and ICC2
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Debug complex physical design challenges involving placement, optimization, clock tree synthesis, routing, and timing closure at advanced nodes where margin is tight and every picosecond counts
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Guide customers through advanced methodologies including AI-driven design techniques, macro placement strategies, and multi-scenario timing closure approaches tailored to their specific project constraints
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Work directly with customer design teams to diagnose tool usage issues, recommend flow improvements, and help them extract maximum performance from Synopsys solutions in production environments
Deliver technical presentations, training sessions, and design reviews that translate tool capabilities into actionable strategies customers can- immediately to their tapeout schedules
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Collaborate with Synopsys sales, R&D, and product teams to communicate customer feedback, reproduce critical issues, and influence product direction based on real-world design challenges
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Stay current on advanced node design requirements, emerging methodologies like H-Tree and MS-CTS, and evolving customer needs across different process technologies and design styles
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Customers will tape out complex designs faster and with better PPA results because you helped them navigate the hardest parts of their physical implementation flow
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Design teams will adopt Synopsys methodologies and tools more deeply, moving from basic usage to advanced techniques that unlock real competitive advantage in their projects
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Synopsys will win and expand customer relationships because you built trust through technical credibility and delivered measurable results when it mattered most
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Product teams will build better tools because you surface the real blockers customers hit in production, not just the issues that show up in benchmarks
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Customer engineering teams will level up their own expertise through the training, guidance, and troubleshooting support you provide during critical project phases
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The broader Synopsys field organization will close deals and grow accounts faster because your technical depth de-risks adoption and proves value in customer environments
Advanced node designs that push the limits of physics and timing will succeed because you helped customers- the right combination of techniques at the right moments in their flow
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Bachelor's degree in Electrical Engineering or equivalent with 7+ years of hands-on ASIC physical design experience, or Master's degree with 5+ years
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Deep experience with RTL-to-GDSII implementation flows using industry-standard tools, including placement, optimization, clock tree synthesis, and routing
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Strong working knowledge of Synopsys backend tools, specifically Fusion Compiler and ICC2, with hands-on experience in logical and physical synthesis, timing closure, and macro placement
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Solid understanding of advanced node design challenges and methodologies, including multi-corner multi-mode timing closure, noise analysis, and routing at 7nm and below
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Demonstrated ability to work directly with customers in technical support or applications engineering roles where you diagnosed real design issues and delivered solutions under pressure
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Experience with Design Compiler for synthesis is a plus, and familiarity with PrimeTime for static timing analysis strengthens your ability to support full-flow engagements
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Knowledge of clock tree synthesis methodologies including H-Tree and MS-CTS approaches is preferred and will help you guide customers through complex clocking challenges
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You can walk into a customer meeting with a failing design, ask three questions, and know whether the issue is a methodology problem, a tool configuration issue, or a fundamental constraint that needs rethinking
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Multiplex is not a buzzword for you, it is how you work because you are managing multiple customer escalations, a product evaluation, and a training prep in the same week without dropping threads
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You communicate complex tradeoffs clearly, whether you are writing up a timing closure strategy for a customer or explaining a routing bottleneck to a sales team that needs to understand risk without getting lost in details
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Customer sensitivity is built into how you operate because you know the engineer you are helping is under deadline pressure, and your job is to make their problem smaller, not add to it
You stay current without being told because you know that what worked at 16nm does not always- at 3nm, and you are the person customers trust to know the difference
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You push back when a proposed solution does not fit the actual problem, and you do it in a way that keeps the relationship strong and the project moving forward
You will be part of the Customer Success Group, the team responsible for helping the world's leading semiconductor companies design and verify advanced silicon chips faster and with better results. This is a global organization that works directly with customers during their most critical design phases, and your role will put you at the center of that work in the Bangalore location supporting regional and global accounts.
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
