Ericsson Jobs

Senior Engineer - ASIC Backend Synthesis
Ericsson —Bengaluru, Karnataka
- Master's degree
- Bachelor's degree
- Scripting
EDA2 L2 Domain Support Specialist
Ericsson —Noida, Uttar Pradesh
- Azure
- Oracle
- Software troubleshooting
GCP Infra Engineer
Ericsson —Noida, Uttar Pradesh
- DevOps
- Java
- Scripting
Experienced Engineer - FPGA CAD
Ericsson —Bengaluru, Karnataka
- English
- Master's degree
- Databases
Senior Engineer/Specialist-Wireline
Ericsson —Noida, Uttar Pradesh
- Oracle
- Computer Science
- Master's degree
Senior Technical Lead
Ericsson —Bengaluru, Karnataka
- Computer Science
- Software troubleshooting
- Master's degree
Senior Technical Authority Expert
Ericsson —Noida, Uttar Pradesh
- B.Sc
- Engineering
- English
Sr. Software Architect- Full stack
Ericsson —Bengaluru, Karnataka
- System design
- Java
- C++
ASIC Top Level Verification-SW/C Testcase Developer
Ericsson —Bengaluru, Karnataka
- Communication skills
Global Business Development Lead - Telco Security
Ericsson —Pune, Maharashtra
- Computer Science
- Engineering
- Master's degree
Lead Engineer - ASIC Verification
Ericsson —Bengaluru, Karnataka
- English
- Electrical experience
- Bachelor's degree
Senior AI Engineer
Ericsson —Bengaluru, Karnataka
- Computer Science
- Master's degree
- AWS
Frontend CAD DV Engineer
Ericsson —Bengaluru, Karnataka
- Computer Science
- B.Sc
- Master's degree
Senior Engineer - Physical Design
Ericsson —Bengaluru, Karnataka
- Master's degree
- Bachelor's degree
- Scripting
5h
Lead Engineer - ASIC Design
Ericsson —Bengaluru, Karnataka
- English
- Electrical experience
- Bachelor's degree
Senior Engineer - ASIC Verification
Ericsson —Bengaluru, Karnataka
- English
- Electrical experience
- Bachelor's degree

Discover related jobs

Based on your search for ericsson jobs.

Part time work from home
Springer Nature —Remote
I need someone who can teach and work well. Job Types: Full-time, Part-time, Fresher Pay: ₹12,000.00 - ₹15,000.00 per month Benefits: * Flexible schedule *…
₹12,000 - ₹15,000 a month
Quick apply
2d
Virtual Relationship Manager (Freshers Eligible)
Client - IDFC First —Thane District, Maharashtra
Serve our most affluent customers & drive growth by ensuring excellent engagement & customer service. Work with internal teams to drive on-ground innovation and…
₹4,00,000 - ₹6,50,000 a year
Quick apply

I want to receive the latest job alerts for ericsson

By signing in to your account, you agree to SimplyHired's Terms of Service and consent to our Cookie and Privacy Policy.

Explore jobs in more locations

ericsson jobs near

Business Development Manager jobs in Pune, Maharashtra

Security Engineer jobs in Noida, Uttar Pradesh

Ai Developer jobs in Bengaluru, Karnataka

Back End Developer jobs in Bengaluru, Karnataka

Lead Engineer jobs in Bengaluru, Karnataka

CAD Technician jobs in Bengaluru, Karnataka

Full Stack Developer jobs in Bengaluru, Karnataka

Lead Designer jobs in Bengaluru, Karnataka

Senior Technical Lead jobs in Bengaluru, Karnataka

Verification Engineer jobs in Bengaluru, Karnataka

Engineering Designer jobs in Pimpri, Pune, Maharashtra

Engineering Designer jobs in Srikakulam, Andhra Pradesh

Engineering Designer jobs in Tamil Nadu

Engineering Designer jobs in Mumbai, Maharashtra

Web Designer jobs in Jaipur, Rajasthan

Freelance Designer jobs in Chennai, Tamil Nadu

Civil Engineering jobs in Andhra Pradesh

Design Engineer jobs in Coimbatore, Tamil Nadu

Design Verification Engineer jobs in Remote

Fpga Engineer jobs in Mumbai, Maharashtra

Senior Engineer - ASIC Backend Synthesis

Ericsson -
Bengaluru, Karnataka

Apply Now

Job details

Qualifications

5G
R
Electronics Engineering
Slack
Master's degree
Bachelor's degree
M.Sc
Scripting
Agile
Communication skills
Python

Full job description

Grow with us

Join Ericsson’s cutting-edge journey to shape the future of 5G networks! As an Physical Synthesis Engineer, you’ll work on pioneering digital ASIC designs vital to Ericsson’s mobile network infrastructure. Our team, responsible for the final critical stage of chip design before fabrication, thrives on Lean and Agile principles, promoting close collaboration, daily progress-sharing, and continuous improvement. If you’re passionate about advanced technology and ready to make a meaningful impact in telecom, this role is crafted just for you.

At Ericsson, we support your growth, offering opportunities to advance your skills while contributing to game-changing 5G/6G technologies. Here, you’ll find a supportive, innovative environment focused on quality, teamwork, and career development. Join us and help shape the future of telecom!

We are hiring a Physical Synthesis Engineer to own the synthesis flow and constraint development on high-performance, low-power SoC designs. Your primary focus will be physical-aware synthesis, floorplan-driven netlist optimization, and QoR closure — while also contributing to static timing analysis (STA) signoff as well. You will work closely with RTL design, place-and-route, and DFT teams throughout the full design cycle.

What you will do:

Physical-Aware Synthesis (PAS)

Execute physical-aware and floorplan-driven synthesis flows to minimize post-layout timing and congestion surprises.
Integrate synthesis with P&R tools for early physical feedback loops — congestion-aware optimization, placement-aware buffering, and pre-CTS timing.
Collaborate with P&R engineers on DEF/floorplan hand-off; iterate on netlist quality to reduce downstream ECO effort.
Perform flat and hierarchical synthesis for large designs; manage partitioning and interface timing budgets.
Perform formal or equivalence check on the netlist at block or top level.

QoR & Optimization

Track and report key QoR metrics — timing slack, area, cell count, power — across design iterations and process corners.
Identify and resolve synthesis bottlenecks: critical path restructuring, datapath optimization, and register retiming.
Provide RTL coding guideline feedback to design teams to improve synthesizability and QoR from the source.
Manage technology library characterization inputs: Liberty (.lib), LEF, and UPF/CPF for multi-voltage designs.
Own synthesis QoR sign-off checklist and contribute to tape-out readiness reviews.

Static Timing Analysis

Run block-level and full-chip STA using PrimeTime (PT) for timing analysis across PVT corners.
Support MMMC (Multi-Mode Multi-Corner) timing closure; analyze and triage timing violations with P&R and synthesis teams.
Review and validate SDC constraints developed during synthesis against post-layout STA results.
Contribute to clock domain crossing (CDC) checks and timing exception audits during signoff.

The skills you bring:

8+ years in physical synthesis or logic design implementation
Expert-level use of Fusion Compiler
Strong SDC constraint authoring and management skills
Experience with physical-aware synthesis flows and P&R hand-off
Working knowledge of STA (PrimeTime)
Proficiency in Tcl; Python scripting a strong plus
At least one tape-out on 7nm or below

Nice to have:

Familiarity with low-power methodologies (UPF/CPF, multi-Vt, clock gating)
Understanding of PTPX-based power analysis flows
DFT synthesis experience (scan, BIST, boundary scan)
Familiarity with congestion-aware and timing-driven P&R closure

EDA Tools & Environment

Design Compiler, Fusion Compiler, Synopsys PrimeTime, Formality, Tcl/Python.

Education & Background

B.Tech / M.Tech / M.S. in Electronics Engineering, VLSI Design, Computer Engineering, or a related field.
Strong foundation in digital logic design, CMOS circuit theory, and standard-cell library concepts.
Excellent scripting and automation skills; comfort with large, multi-million gate designs.
Strong communication skills — able to clearly present QoR status, risks, and trade-offs to cross-functional teams.

.

“All academic credentials must be from recognized and accredited institutions and are further subject to verification.”

Why join Ericsson?At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.

What happens once you apply?Click Here to find all you need to know about what our typical hiring process looks like.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.

Primary country and city: India (IN) || Bangalore

Req ID: 783577

Apply Now

Refine Your Search

Senior Engineer - ASIC Backend Synthesis

EDA2 L2 Domain Support Specialist

GCP Infra Engineer

Experienced Engineer - FPGA CAD

Senior Engineer/Specialist-Wireline

Senior Technical Lead

Senior Technical Authority Expert

Sr. Software Architect- Full stack

ASIC Top Level Verification-SW/C Testcase Developer

Global Business Development Lead - Telco Security

Lead Engineer - ASIC Verification

Senior AI Engineer

Frontend CAD DV Engineer

Senior Engineer - Physical Design

Lead Engineer - ASIC Design

Senior Engineer - ASIC Verification

Discover related jobs

I want to receive the latest job alerts for ericsson

Explore jobs in more locations

Grow with us

What you will do:

The skills you bring:

Nice to have:

Education & Background

.

Jobseeker tools

Employer Tools

Browse

Stay Connected