The Hard IP Development Group (HIPD) within Central Engineering Organization of Intel is responsible for developing leadership IPs that power-winning products for Server, Client, Networking SOCs as well as Intel Foundry Customers. HIPD group develops a broad portfolio of IPs like PLLs, Serial and Parallel IO PHYs like DDR/LPDDR, PCIe, USB, TypeC, UCIe Die 2 Die and Ethernet PHYs.
The IO Post Silicon validation debug group within HIPD team is a dynamic and versatile team of engineers who directly engage with both the IP design teams and SOC customers in IP validation and debug for test chips and products. These engineers will embody our SOC customer obsession by quickly resolving IP related hurdles by providing hands on debug. This position is exciting and challenging to exercise your mixed signal design, architecture and post silicon debug expertise across IP and SOC teams.
Your responsibilities will include but are not limited to:
Work closely with SOC customers and IP design teams to provide pre silicon to post silicon IP design characterizations, generating the test plans and test contents using AI driven tools and pythonSV scripting, SOC board design reviews and recommendations, Signal and Power Integrity simulations and post silicon debugs etc.
Represent the IP team during SOC Power Ons for test chips and products and provide hands on IP enabling support
Identify IP related silicon issues, investigate, debug and disposition customer bugs/sightings in a timely manner.
Carry out pre silicon and post silicon reproduction of the issue and work towards to root cause with failure analysis etc...
Minimum Qualifications:
Must have a BS or MS or PhD in Computer Engineering or Electrical Engineering or a Related Field.
Minimum 6+ years of experience in Electrical or Functional Post Silicon validation and debug with either serial IOs (PCIe, USB, SATA, TypeC, Ethernet) or parallel IOs (DDR, LPDDR, UCIe Die2Die).
Well versed with the lab hardware and software is must. Must be proficient in using Oscilloscopes, Logic Analyzers, Protocol analyzers and BERTs.
Familiarity with at least one or more industry standard IO specifications like DDR, LPDDR, PCIE, USB, USB TypeC, Die2Die, Ethernet, etc. Either PHY or Controller experience is good.
Desired Qualifications:
Able to lead on IP debug as situation arises in addition to hands on debug
Good understanding of signal integrity and power delivery are desired
Pre silicon design or simulation experience in logic, circuits, firmware or MRC and mixed signal validation will be a plus.
Experienced Hire
Shift 1 (India)
India, Bangalore
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
