Senior/staff analog design engineer Jobs

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- Management
- B.Sc
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- Full-time
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- Data analysis skills
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Qualcomm —Noida, Uttar Pradesh
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Texas Instruments —Bengaluru, Karnataka
- C++
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Renesas Electronics —Bengaluru, Karnataka
- Full-time
- Hybrid work
- Computer Science
- Master's degree
- Bachelor's degree
Quick apply
Staff /Sr Staff Application Engineering (Motor)
Renesas Electronics —Bengaluru, Karnataka
- Full-time
- Remote
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Sr Principal Engineer - Validation
Renesas Electronics —Hyderabad, Telangana
- Full-time
- Remote
- Master's degree
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Spacelabs —Madhapur, Hyderabad, Telangana
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Synopsys —India
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Microchip Technology —Bengaluru, Karnataka
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Staff Analog/Mixed-Signal Design Engineer

Synopsys -
Bengaluru, Karnataka

Apply Now

Job details

Qualifications

Management
B.Sc
Verilog
Electrical experience
Bachelor's degree
SystemVerilog
Electrical Engineering
Communication skills

Full job description

Date posted 04/29/2026

Category Engineering Hire Type Employee Job ID 17060 Remote Eligible No Date Posted 04/29/2026

Synopsys is at the heart of all the advanced silicon design, we supply the essential tools and intellectual properties to enable semiconductor design, verification, and production. We’re powering all state-of-the-art design market with the world’s most advanced technologies for chip design and software security.

LPDDR PHY IP is a staple of the mixed-signal IP market, and Synopsys is the leading provider of LPDDR PHY IP products. All current and next-generation technologies are being developed by the LPDDR PHY IP team, both digital and analog components, complement each other in creating a high-performance, high-bandwidth, low-latency and low-power products.

We are looking for an ASIC Digital Design Sr. Manager to join Synopsys LPDDR PHY IP team to lead innovation and development of the world-class market-leading DesignWare LPDDR PHY IP solution.

Job Description

Be part of a global diverse team that pushes boundaries on DDR PHY IP development and solution
Your passion and expertise will shape the next generation of product innovation, performance, and efficiency
You will manage a team of design engineers and work with Architect, Verification, Physical implementation, and Firmware teams
In this role, you will contribute to all phases of designs of DDR PHY IP from design specification to productization, including certain level of customer support into their SoCs
You will lead the team to deliver the design and achieve the best timing, performance, and power goals

Required Skills

BS in Electrical Engineering with at least 12-15 years of experience in complex technical development
2 years of experience in people management, developing employees
Experience with synthesizable Verilog and System Verilog design concepts and implementation
Experience with front-end design flows including linting, synthesis, STA, cross-domain clocking, DFT, and power optimization techniques
Exhibit excellent communication skills and be self-motivated
Understanding of memory and memory PHY architecture is a plus

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Apply Now

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Category Engineering Hire Type Employee Job ID 17060 Remote Eligible No Date Posted 04/29/2026

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