<h1><b>Job Details:</b></h1><p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Job Description: </h2><p>Intel is seeking a Design Verification Engineer for the Silicon Chassis team. In this role, you will independently own verification of interconnect and chassis IP blocks from planning through coverage closure, operating with minimal guidance. You will build and drive robust verification plans, develop scalable reusable environments, and take direct accountability for quality and schedule on your assigned blocks. You will work closely with architecture, design, and software teams and are expected to contribute across traditional discipline boundaries. This role requires strong DV depth, solid protocol knowledge, hands-on coding strength, and growing ability to mentor junior engineers. AI-assisted workflows are part of everyday development here. Consistent execution against schedule and quality goals is expected.<br /><br />Responsibilities:</p><p><br />- Own verification planning and execution for assigned IP blocks and features at IP and subsystem level; drive test plans through coverage closure with direct accountability for quality.<br />- Build scalable verification environments with reusable testbenches, checkers, constrained-random tests, and debug infrastructure; take ownership of the verification collateral you deliver.<br />- Collaborate closely with architecture, design, and software teams on spec reviews, feature clarification, bug triage, and closure; contribute outside strict DV boundaries when needed to unblock progress.<br />- Analyze simulation failures, root-cause issues quickly, and drive fixes to closure with clear technical communication; own debug for your blocks end-to-end.<br />- Drive functional coverage planning and coverage closure for assigned blocks; contribute to quality signoff with increasing independence.<br />- Contribute to both simulation and formal verification efforts; continuously improve verification automation, regression quality, and development efficiency.<br />- Begin mentoring junior engineers on verification practices, debugging techniques, and code quality.</p><p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2><b>Qualifications:</b></h2><p>Minimum Qualifications-</p><p><br />- BS/MS in Electrical Engineering, Computer Science, or related field, with 8-12 years of relevant experience in design verification; solid background in IP-level DV with meaningful exposure to subsystem-level verification<br />- Strong and growing expertise in interconnects and bus protocols such as AMBA AXI/ACE/CHI, PCIe, CXL, or UCIe; working understanding of cache coherency and memory consistency models<br />- Strong background in simulation-based verification methodologies including UVM, SVA, and ABV; hands-on testbench development, debugging, and coverage-driven verification<br />- Hands-on coding proficiency across System Verilog/UVM, C/C++, and Python; track record of delivering clean, reusable, and maintainable verification code and automation scripts<br />- Comfort using AI-assisted development tools as part of everyday workflow for coding, debugging, and test development<br />- Ability to collaborate effectively across architecture, design, and software teams; enough context outside core DV to contribute meaningfully when needed<br /><br />Preferred Qualifications-</p><p><br />- Experience with formal verification tools (JasperGold, VC Formal, or similar) and emulation or FPGA-based verification<br />- Exposure to verification of global functions such as debug, trace, clock and power management, RAS, or security features<br />- Working familiarity with RTL concepts, physical design, or CAD tool flows<br />- Prior work with system IPs such as MMUs (SMMU or IOMMU) and interrupt controller</p><p></p><p> </p><p></p><p></p><h2>Job Type:</h2>Experienced Hire<p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Shift:</h2>Shift 1 (India)<p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Primary Location: </h2>Virtual India<p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Additional Locations:</h2><p style="text-align:inherit"></p><p style="text-align:inherit"></p><p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Business group:</h2>The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.<p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Posting Statement:</h2>All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.<h2></h2><h2>Position of Trust</h2>N/A<p style="text-align:inherit"></p><p style="text-align:left"><b>Work Model for this Role</b></p>This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. * Job posting details (such as work model, location or time type) are subject to change.<p></p><p>*</p><p></p>ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
