<h1><b>Job Details:</b></h1><p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Job Description: </h2><ul><li>Performs functional verification of IP logic to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications.</li><li>Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs.</li><li>Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features.</li><li>Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.</li><li>Maintains and improves existing functional verification infrastructure and methodology.</li><li>Participates in the definition of verification infrastructure and related TFMs needed for functional design verification.</li></ul><p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2><b>Qualifications:</b></h2><p>Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.</p><p></p><p><b><span>Bachelor's Degree with 3-7 years of experience.</span> </b><br /><br />Minimum Qualifications:<br />1. Very good perl, python (or) any programming language.<br />2. Excellent in system Verilog<br />3. Very good in computer architecture.<br />4. Exposure to AMBA protocols preferred.<br /><br />Preferred Qualifications:<br />• Bringing up coherent protocols from 0 to1.<br />• 1 years of Experience on Network on Chip verification.<br />• 1 years of experience developing protocol checkers, bridge checkers, VIP integration,<br />• Configurable IP verification.<br />• Strong in coherency architecture and experience on Coherent Protocols CHI<br /><br />Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.</p><p></p><p> </p><p></p><p></p><h2>Job Type:</h2>Experienced Hire<p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Shift:</h2>Shift 1 (India)<p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Primary Location: </h2>India, Bangalore<p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Additional Locations:</h2><p style="text-align:inherit"></p><p style="text-align:inherit"></p><p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Business group:</h2>The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.<p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Posting Statement:</h2>All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.<h2></h2><h2>Position of Trust</h2>N/A<p style="text-align:inherit"></p><p style="text-align:left"><b>Work Model for this Role</b></p>This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.<p></p><p>*</p><p></p>ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
