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IC Technology Development Lead Frame/substrate design Manager

Tata Electronics -
Karnataka

Apply Now

Job details

Qualifications

AutoCAD
Schematics
English
Master's degree
Electrical experience
Presentation skills
Bachelor's degree
Embedded software
Manufacturing

Full job description

IC Technology Development Lead Frame/substrate design Manager

Job ID:

39314

Job ID:

39314

Date:

16 May 2026

Date:

16 May 2026

Location:

Vemagal, KA, IN

Location:

Vemagal, KA, IN

Department:

Assembly Technology Development

Department:

Assembly Technology Development

Business:

TSAT India

Business:

TSAT India

About The Business:

Tata Electronics Private Limited (TEPL) is a greenfield venture of the Tata Group with expertise in manufacturing precision components.

Tata Electronics (a wholly owned subsidiary of Tata Sons Pvt. Ltd.) is building India’s first AI-enabled state-of-the-art Semiconductor Foundry. This facility will produce chips for applications such as power management IC, display drivers, microcontrollers (MCU) and high-performance computing logic, addressing the growing demand in markets such as automotive, computing and data storage, wireless communications and artificial intelligence. Tata Electronics is a subsidiary of the Tata group.

The Tata Group operates in more than 100 countries across six continents, with the mission 'To improve the quality of life of the communities we serve globally, through long term stakeholder value creation based on leadership with Trust.’

Responsibilities:

Perform logical packaging design (interpreting and creating netlist, ball pad layout and routing rules from customer provided information packages and schematics).
Perform substrate layout design & stack- up analysis (parts placement, line/space routing, design rule check etc.)
Design for feasibility / manufacturability / Cost – work with substrate suppliers, apply best industry practices to reduce cost and maximize substrate yield and meet industrial design standards such as JEDEC standards.
Verify new internal design tools and feedback to development team and perform sign off.
Create design documents and develop training manual.

Essential Attributes:

Proficient in Cadence Allegro Package Designer (APD) or comparable & AutoCAD experience to design, view, edit or verify designs for optimization iterations and package sign-off.
Working knowledge in logical net-listings, schematics usage, electrical and routing rules creation.
Experience in designs utilizing blind, buried and micro vias would be advantageous.
Good understanding on enabling high-density interconnects, associated mechanical, thermal and reliability issues.
Good understanding on creating design manual, design rules, generation rules, drawings preparation and documentation.
Good understanding & knowledge on Advanced Packaging architecture and semiconductor packaging process flow (Back Grinding, Dicing, Die Attach, Wire Bonding, Moulding, P&P, Ball Attach, Trim & Form, Singulation).
Strong presentation skills with excellent networking skills.
Excellent English communication to work with a diverse cross-functional culture.

Qualifications:

Bachelor or Master Degree in Electrical, Mechanical, or Materials Science Engineering.

Desired Experience Level:

Minimum 5 to 10 years of experience in semiconductor packaging & substrate designing.

About The Business:

Tata Electronics Private Limited (TEPL) is a greenfield venture of the Tata Group with expertise in manufacturing precision components.

Responsibilities:

Perform logical packaging design (interpreting and creating netlist, ball pad layout and routing rules from customer provided information packages and schematics).
Perform substrate layout design & stack- up analysis (parts placement, line/space routing, design rule check etc.)
Design for feasibility / manufacturability / Cost – work with substrate suppliers, apply best industry practices to reduce cost and maximize substrate yield and meet industrial design standards such as JEDEC standards.
Verify new internal design tools and feedback to development team and perform sign off.
Create design documents and develop training manual.

Essential Attributes:

Proficient in Cadence Allegro Package Designer (APD) or comparable & AutoCAD experience to design, view, edit or verify designs for optimization iterations and package sign-off.
Working knowledge in logical net-listings, schematics usage, electrical and routing rules creation.
Experience in designs utilizing blind, buried and micro vias would be advantageous.
Good understanding on enabling high-density interconnects, associated mechanical, thermal and reliability issues.
Good understanding on creating design manual, design rules, generation rules, drawings preparation and documentation.
Good understanding & knowledge on Advanced Packaging architecture and semiconductor packaging process flow (Back Grinding, Dicing, Die Attach, Wire Bonding, Moulding, P&P, Ball Attach, Trim & Form, Singulation).
Strong presentation skills with excellent networking skills.
Excellent English communication to work with a diverse cross-functional culture.

Qualifications:

Bachelor or Master Degree in Electrical, Mechanical, or Materials Science Engineering.

Desired Experience Level:

Minimum 5 to 10 years of experience in semiconductor packaging & substrate designing.

Learn More about TATA Electronics

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Learn More About Tata Electronics

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