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Analog / Mixed-Signal Layout Engineer

ARASAN CHIP SYSTEMS INC -
Remote

Quick apply

Job details

Full-time
₹5,00,000 - ₹15,00,000 a year
4 hours ago

Benefits

Cell phone reimbursement
Work from home
Flexible schedule
Food provided

Qualifications

Node.js
BSEE
B.Sc
Git
Master's degree
Assembly
Science
Bachelor's degree
ANSYS
M.Sc
Scripting
Macros
B.E.
Electrical Engineering
Python

Full job description

Department:

IC Design / Silicon Engineering

Function:

Analog/Mixed-Signal Physical Design

Education:

B.E (Electronics and Communication Engineering or Electrical and Electronics Engineering) - Required

Experience:

3+ Years in Analog/Mixed-Signal IC Layout

Employment Type:

Full-Time | Permanent

Position Summary

We are seeking a highly skilled and motivated Analog/Mixed-Signal Layout Engineer with a minimum of 3 years of hands-on experience in the physical design of complex analog and mixed-signal integrated circuits. The successful candidate will collaborate closely with circuit designers to develop, implement, and verify full-custom layouts for a broad range of analog macros across advanced CMOS process nodes. This role demands deep understanding of transistor-level design, parasitic effects, high-frequency layout techniques, and a meticulous attention to detail.

Circuit Design Scope

The engineer will be responsible for designing and implementing layouts across the following analog and mixed-signal macro categories:

Receivers (RX)

CDR

LDOs

Bandgap References

POR

Oscillators

Charge Pumps

UV/OV Protection

DC-DC Converters

Analog Switches

Transmitters (TX)

DLL

Bias Generators

Clocking Circuits

PLLs

Diff Amplifiers

Comparators

Mixed-Signal I/Os

Key Responsibilities

Physical Layout Design

▸ Perform full-custom layout of analog and mixed-signal macros from schematic to GDSII using Cadence Virtuoso or equivalent EDA toolsuite

▸ Implement device-level layouts with precision matching techniques: common-centroid, interdigitation, and dummy device insertion

▸ Design compact and high-performance layouts for circuits including LDOs, bandgap references, oscillators, charge pumps, and clocking circuits

▸ Develop layout for high-speed SerDes sub-blocks including TX drivers, RX front-ends, CDR loops, and DLL circuits

▸ Execute power-sensitive layouts for DC-DC switching converters, bias generators, and UV/OV protection circuits

Verification & Sign-Off

▸ Run and resolve DRC (Design Rule Check), LVS (Layout vs. Schematic), and ERC (Electrical Rule Check) using Mentor Calibre, Synopsys IC Validator, or equivalent

▸ Perform parasitic extraction (RCX/PEX) and co-analyze post-layout simulation results with design engineers to meet performance targets

▸ Conduct antenna rule checks, density checks, and CMP-related fill strategies per foundry requirements

▸ Support the full tapeout flow through to GDSII sign-off, including final quality-of-results reviews

Collaboration & Documentation

▸ Collaborate with circuit designers to understand design intent, performance targets, and floorplanning requirements

▸ Contribute to layout guidelines, best-practice documentation, and IP reuse frameworks

▸ Participate in design reviews, floorplan reviews, and inter-team technical discussions

▸ Mentor junior layout engineers and contribute to team capability development

Process & Technology

▸ Work across multiple foundry process nodes (28nm, 16nm, 7nm, and below), adhering to process-specific design rules and recommendations

▸ Engage with foundry PDK teams and process engineers to resolve technology-specific layout challenges

▸ Apply electromigration (EM) and IR-drop analysis guidelines in power delivery network (PDN) design

Required Qualifications

▸ Bachelor of Science in Electrical Engineering (BSEE) – Mandatory

▸ Minimum 3 years of professional experience in analog/mixed-signal IC layout design

▸ Proficiency with Cadence Virtuoso Layout Suite (GXL or XL) and associated Virtuoso ADE environment

▸ Hands-on experience with Calibre DRC/LVS/PEX or IC Validator

▸ Strong understanding of MOSFET device physics, parasitic capacitances, and their impact on circuit performance

▸ Demonstrated experience laying out at least 3 of the circuit types listed in the Circuit Design Scope section

▸ Solid knowledge of analog layout techniques: symmetry, shielding, substrate isolation, guard rings, and latch-up prevention

▸ Familiarity with FinFET or GAA process node layout constraints

Preferred Qualifications

▸ M.S. in Electrical Engineering with emphasis on analog/mixed-signal circuits or VLSI design

▸ Experience with high-speed interfaces: PCIe, USB, DDR, MIPI, or SerDes at 10Gbps+

▸ Exposure to GDS stream-out, tapeout coordination, and multi-project wafer (MPW) processes

▸ Familiarity with Python or SKILL scripting for layout automation and custom pcell development

▸ Knowledge of mixed-signal floor planning and top-level chip assembly

▸ Experience with power integrity analysis tools (Voltus, RedHawk, or equivalent)

▸ Prior collaboration with foundries such as TSMC, Samsung, GlobalFoundries, or UMC

Technical Skills Matrix

Category

Tools / Technologies

Proficiency Level

EDA Layout Tool - Cadence Virtuoso (GXL/XL) - Required – Expert

DRC / LVS / ERC - Pegasus, Mentor Calibre, IC Validator - Required – Proficient

Parasitic Extraction - Calibre xRC, StarRC, Quantus - Required – Proficient

Process Nodes - 28nm / 16nm FinFET / 7nm+ - Required – 1+ nodes

Scripting / Automation - SKILL, Python, OCEAN - Preferred

Power Integrity - Voltus, RedHawk, ANSYS - Preferred

Simulation Verification - Cadence Spectre, HSPICE - Preferred

Version Control - SOS, GIT - Preferred

What We Offer

▸ Competitive compensation package with performance-linked incentives

▸ Opportunity to work on cutting-edge semiconductor products across diverse application domains

▸ Access to industry-leading EDA tools and advanced process node PDKs

▸ Collaborative and technically challenging work environment with world-class IC designers

Pay: ₹500,000.00 - ₹1,500,000.00 per year

Benefits:

Cell phone reimbursement
Flexible schedule
Food provided
Work from home

Work Location: Remote

Quick apply

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expert python engineer jobs in remote india

Analog / Mixed-Signal Layout Engineer

Associate Python Engineer

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