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Sr Physical Design Engineer

Synopsys -
Noida, Uttar Pradesh

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Job details

Qualifications

Electronics Engineering
Master's degree
Bachelor's degree
Perl
Scripting
Electrical Engineering
Python

Full job description

Date posted 05/05/2026

Category Engineering Hire Type Employee Job ID 17266 Remote Eligible No Date Posted 05/05/2026

ASIC Physical Design Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent the last few years deep in the physical implementation trenches, turning RTL into actual silicon that works at the latest nodes. You know that the difference between a chip that tapes out clean and one that comes back with timing violations is usually a decision you made during floorplanning or a constraint you wrote three weeks earlier. You are the kind of engineer who catches those decisions before they become problems.

You do not just run tools, you understand what they are doing under the hood. When PrimeTime flags a violation, you know whether it is real or a false path before you even open the timing report. You have debugged enough EM/IR issues to know that power planning is not something you fix at the end, it is something you build correctly from the start.

You are comfortable working across the full flow, from synthesis through signoff, and you can script your way out of repetitive work without being asked. You think in terms of methodology, not just milestones. At Synopsys, you will work on high-performance interface IPs and test chips at nodes where the margin for error is measured in picoseconds, and the team will expect you to know what you are doing.

What You'll Be Doing

Own end-to-end physical implementation for high-performance interface IPs and test chips, taking designs from RTL through synthesis, floorplanning, placement, CTS, routing, and signoff to GDS
Develop and refine timing constraints, perform static timing analysis using PrimeTime, and close timing across multiple corners and modes at advanced nodes
Execute power planning, run EM/IR analysis using RedHawk, and ensure power integrity and reliability signoff for complex subsystem designs
Perform physical verification using ICV, resolve DRC/LVS issues, and coordinate with foundry teams to ensure manufacturability
Build and improve implementation flows and CAD methodologies using Tcl, Perl, and Python scripting to automate repetitive tasks and increase design productivity
Collaborate with front-end design, DFT, and verification teams to resolve design issues, optimize for area, power, and performance, and drive designs to tape-out
Contribute to subsystem-level integration efforts, working across multiple IP blocks to ensure clean hierarchical implementation and signoff

The Impact You Will Have

Your implementation work will directly enable tape-outs of high-performance interface IPs used in cutting-edge semiconductor products across the industry
The flows and methodologies you build will be reused across multiple projects, improving turnaround time and quality for the entire physical design team
Your timing closure and signoff rigor will reduce the risk of silicon respins, saving months of schedule and significant engineering cost
The scripts and automation you create will free up engineering time across the team, letting others focus on harder problems instead of manual grunt work
Your collaboration with front-end and verification teams will catch design issues earlier, reducing costly iterations late in the implementation cycle
The subsystem integration work you lead will enable larger, more complex designs to be delivered on aggressive schedules
Your expertise will help define best practices and mentor junior engineers as the team scales to support more projects at advanced nodes

What You'll Need

Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, VLSI Design, or equivalent technical field
3 to 5 years of hands-on experience in ASIC physical implementation, with at least one recent project tape-out to your name
Strong working knowledge of Synopsys tools including Design Compiler, ICC2 or Fusion Compiler, PrimeTime, Star-RCXT, ICV, and RedHawk
Solid understanding of deep sub-micron design challenges including timing closure, power integrity, EM/IR analysis, and physical verification at 16nm or below
Proficiency in scripting languages such as Tcl, Perl, or Python for automation and flow development
Experience with IP subsystem implementation or hierarchical design flows is a strong plus
Familiarity with timing constraint development, multi-mode multi-corner analysis, and signoff methodologies

Who You Are

You can look at a floorplan and immediately spot the congestion hotspots, the clock distribution challenges, and the power delivery risks before you even start placement
You write timing constraints that are tight enough to catch real issues but not so conservative that you are chasing false violations for three weeks
You do not wait for someone to tell you to automate a task you have done manually twice, by the third time you have already written the script
You can explain a timing path failure to a front-end designer in two sentences without losing the technical nuance, and you know when to push back on an unrealistic constraint
You stay current with what is changing at advanced nodes, whether it is new DFM rules, updated signoff requirements, or tool updates that actually matter
You are organized enough to manage multiple blocks through different stages of the flow simultaneously without dropping details or missing handoff deadlines

The Team You'll Be Part Of

Your recruiter will

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