Delhi Delhi Test engineer Jobs – 155 Open Jobs Today

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R&D Engineering, Sr Staff Engineer - Design Verification/ VIP Verification Engineers

Synopsys -
Delhi, Delhi

Apply Now

Job details

2 hours ago

Qualifications

Computer Science
Software deployment
Electronics Engineering
Master's degree
Analysis skills
Bachelor's degree
Ethernet
SystemVerilog
Debugging

Full job description

Date posted 06/03/2026

Category Engineering Hire Type Employee Job ID 17694 Remote Eligible No Date Posted 06/03/2026

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years building Verification IP that engineers actually trust, not just IP that passes a checklist. The difference matters to you because you know a VIP is only as good as the edge cases it catches and the clarity it brings when something breaks at 2 a.m. in a customer lab. Debugging a protocol violation three layers deep does not frustrate you, it pulls you in because finding the root cause matters more than closing a ticket.

When you read a protocol specification, you are already mapping out the sequences that will stress the implementation in ways the design team has not considered yet. You think in coverage metrics and edge cases. Working with AMBA, PCIe, Ethernet, DFI, or DRAM protocols long enough has taught you where the gaps usually hide and what good verification architecture looks like when it scales across products and customers.

Deploying directly with customers does not feel like a distraction, it feels like the part where you learn what actually matters. Bringing tasks to closure is non-negotiable because leaving something half done keeps you up at night. At Synopsys, you will work with protocol experts, Design IP teams, and industry-leading verification tools. What you build will ship into semiconductor development workflows across the industry.

What You'll Be Doing

Design, develop, and maintain Verification IP using SystemVerilog and UVM for industry-standard protocols including DFI, DRAM, AMBA, PCIe, USB, and Ethernet
Build comprehensive verification plans that map protocol specifications to testable scenarios, coverage goals, and corner case strategies
Code sequences, test scenarios, and checkers that drive coverage-based verification across functional and code coverage dimensions
Debug complex simulation failures across multi-layer protocol stacks, identifying root causes in both VIP logic and customer integration environments
Enhance existing VIP products for performance, reusability, and scalability as protocols evolve and customer use cases expand
Support customers during VIP integration and deployment, troubleshooting issues, answering technical questions, and ensuring successful bring-up
Collaborate with Design IP teams, R&D engineers, and field application teams to align VIP capabilities with product roadmaps and customer needs

The Impact You Will Have

Your VIP will enable faster, more reliable verification for semiconductor companies building next-generation SoCs and AI-powered products
Coverage-driven verification strategies you implement will catch critical protocol violations before they reach silicon, saving months of debug time downstream
Enhancements you make to existing VIP products will improve performance and expand protocol support across the Synopsys IP portfolio
Customer deployments you support will directly influence how engineers at leading semiconductor companies adopt and trust Synopsys VIP
Verification plans you create will set the standard for how protocol compliance is validated across complex, multi-protocol designs
Collaboration with Design IP teams will tighten the feedback loop between design and verification, improving quality across both disciplines
Your work will contribute to a VIP product line used globally in semiconductor development, affecting how chips are verified at scale

What You'll Need

Bachelor's or Master's degree in Electronics Engineering, Computer Science, or equivalent practical experience
5+ years of hands-on experience developing Verification IP or SystemVerilog/UVM-based test benches
Deep working knowledge of at least two industry-standard protocols such as AMBA (AXI, AHB, APB), DFI, DRAM, PCIe, or Ethernet
Strong proficiency in SystemVerilog and UVM methodology for building reusable, scalable verification environments
Demonstrated ability to create and execute coverage-driven verification plans, including functional and code coverage analysis
Experience debugging complex simulation failures and resolving issues across protocol layers and integration boundaries
Experience working directly with customers or field teams during product deployment is a strong plus

Who You Are

You can read a protocol specification and translate it into a verification plan that covers not just the happy path but the corner cases that break real designs
Debugging a failing sequence across thousands of lines of log output does not drain you, it engages you because you know the answer is in there somewhere
You bring strong opinions about what good VIP architecture looks like, and you are willing to push back when a shortcut will create technical debt six months from now
Working with customers during integration feels like a natural extension of your work, not a context switch, because you want to see your VIP succeed in the field
You are organized enough to manage multiple VIP enhancements, customer issues, and verification plans in parallel without losing track of quality or deadlines
When a task is 90% done, you are owning the final 10%, validating outcomes, tightening documentation, and ensuring complete, high-quality delivery

The Team You'll Be Part Of

Your recruiter will

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Category Engineering Hire Type Employee Job ID 17694 Remote Eligible No Date Posted 06/03/2026

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