Ericsson Jobs

Experienced Engineer - ASIC Backend Synthesis
Ericsson —Bengaluru, Karnataka
- Scripting
- Agile
- Python
6h
Lead Engineer - ASIC Design
Ericsson —Bengaluru, Karnataka
- English
- Electrical experience
- Bachelor's degree

More jobs to discover

Find similar jobs that you might be interested in.

Lead Engineer - ASIC Design
Ericsson —Bengaluru, Karnataka
12+ years of industry experience in ASIC design. Lead a team of design engineers, providing mentorship and guidance to ensure efficient and reusable design…
Mixed Signal Staff Enginee
Synopsys —Bengaluru, Karnataka
Your curiosity drives you to explore industry standards such as JEDEC DDR interfaces, and you are comfortable navigating the complexities of ASIC design flows.

I want to receive the latest job alerts for ericsson

By signing in to your account, you agree to SimplyHired's Terms of Service and consent to our Cookie and Privacy Policy.

Explore jobs in more locations

ericsson jobs near

Lead Designer jobs in Bengaluru, Karnataka

Back End Developer jobs in Bengaluru, Karnataka

Graphic Designer, Location jobs in Rohtak, Haryana

Lead Designer jobs in Ahmedabad, Gujarat

Lead Designer jobs in Remote

Interior Designer jobs in Delhi, Delhi

Lead Designer jobs in Delhi, Delhi

Graphic Designer, Ngo jobs in Remote

Lead Designer jobs in Chennai, Tamil Nadu

Ui Ux Designer jobs in Chennai, Tamil Nadu

Back Office, Billing jobs in Jalandhar, Punjab

Fresher Developer jobs in Kochi, Kerala

Back End Developer jobs in Kerala

Back End Developer jobs in Tirunelveli, Tamil Nadu

Sap End User jobs in Bengaluru, Karnataka

Front End Developer Fresher jobs in Chennai, Tamil Nadu

Back End Developer jobs in Bhopal, Madhya Pradesh

Experienced Engineer - ASIC Backend Synthesis

Ericsson -
Bengaluru, Karnataka

Apply Now

Job details

6 hours ago

Qualifications

5G
R
Slack
Scripting
Agile
Python

Full job description

Grow with us

Join Ericsson’s cutting-edge journey to shape the future of 5G networks! As an Physical Synthesis Engineer, you’ll work on pioneering digital ASIC designs vital to Ericsson’s mobile network infrastructure. Our team, responsible for the final critical stage of chip design before fabrication, thrives on Lean and Agile principles, promoting close collaboration, daily progress-sharing, and continuous improvement. If you’re passionate about advanced technology and ready to make a meaningful impact in telecom, this role is crafted just for you.

At Ericsson, we support your growth, offering opportunities to advance your skills while contributing to game-changing 5G/6G technologies. Here, you’ll find a supportive, innovative environment focused on quality, teamwork, and career development. Join us and help shape the future of telecom!

We are hiring a Physical Synthesis Engineer to own the synthesis flow and constraint development on high-performance, low-power SoC designs. Your primary focus will be physical-aware synthesis, floorplan-driven netlist optimization, and QoR closure — while also contributing to static timing analysis (STA) signoff as well. You will work closely with RTL design, place-and-route, and DFT teams throughout the full design cycle.

What you will do:

Physical-Aware Synthesis (PAS)

Execute physical-aware and floorplan-driven synthesis flows to minimize post-layout timing and congestion surprises.
Integrate synthesis with P&R tools for early physical feedback loops — congestion-aware optimization, placement-aware buffering, and pre-CTS timing.
Collaborate with P&R engineers on DEF/floorplan hand-off; iterate on netlist quality to reduce downstream ECO effort.
Perform flat and hierarchical synthesis for large designs; manage partitioning and interface timing budgets.
Perform formal or equivalence check on the netlist at block or top level.

QoR & Optimization

Track and report key QoR metrics — timing slack, area, cell count, power — across design iterations and process corners.
Identify and resolve synthesis bottlenecks: critical path restructuring, datapath optimization, and register retiming.
Provide RTL coding guideline feedback to design teams to improve synthesizability and QoR from the source.
Manage technology library characterization inputs: Liberty (.lib), LEF, and UPF/CPF for multi-voltage designs.
Own synthesis QoR sign-off checklist and contribute to tape-out readiness reviews.

Static Timing Analysis

Run block-level and full-chip STA using PrimeTime (PT) for timing analysis across PVT corners.
Support MMMC (Multi-Mode Multi-Corner) timing closure; analyze and triage timing violations with P&R and synthesis teams.
Review and validate SDC constraints developed during synthesis against post-layout STA results.
Contribute to clock domain crossing (CDC) checks and timing exception audits during signoff.

The skill you bring:

5+ years in physical synthesis or logic design implementation
Expert-level use of Fusion Compiler
Strong SDC constraint authoring and management skills
Experience with physical-aware synthesis flows and P&R hand-off
Working knowledge of STA (PrimeTime)
Proficiency in Tcl; Python scripting a strong plus
At least one tape-out on 7nm or below

Nice to have:

Familiarity with low-power methodologies (UPF/CPF, multi-Vt, clock gating)
Understanding of PTPX-based power analysis flows
DFT synthesis experience (scan, BIST, boundary scan)
Familiarity with congestion-aware and timing-driven P&R closure

EDA Tools & Environment

Design Compiler, Fusion Compiler, Synopsys PrimeTime, Formality, Tcl/Python.

.

“All academic credentials must be from recognized and accredited institutions and are further subject to verification.”

What happens once you apply?Click Here to find all you need to know about what our typical hiring process looks like.We encourage you to consider applying to jobs where you might not meet all the criteria. We recognize that we all have transferrable skills, and we can support you with the skills that you need to develop.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.

Primary country and city: India (IN) ||

Job details: Developer

Job Stage: Job Stage 5

Primary Recruiter: Ashwini Manda

Hiring Manager: Govinda Raju

[[cust_PostingSalary]]

[[custposttext4]] [[custposttext5]]

[[custposttext]] [[custposttext1]] [[custposttext2]] [[custposttext3]]

Apply Now

Refine Your Search

Experienced Engineer - ASIC Backend Synthesis

Lead Engineer - ASIC Design

More jobs to discover

I want to receive the latest job alerts for ericsson

Explore jobs in more locations

Grow with us

What you will do:

The skill you bring:

Nice to have:

.

Jobseeker tools

Employer Tools

Browse

Stay Connected