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ASIC Digital Design, Principal Engineer

Synopsys -
Noida, Uttar Pradesh

Apply Now

Job details

Benefits

Health insurance

Qualifications

Electronics Engineering
Master's degree
Bachelor's degree
Perl
Scripting
Electrical Engineering
Python
Debugging

Full job description

Date posted 06/15/2026

Category Engineering Hire Type Employee Job ID 17830 Remote Eligible No Date Posted 06/15/2026

Alternate Job Titles

Design for Test Staff Engineer
DFT Implementation Staff Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years thinking about how chips break and how to catch those failures before they reach a customer. Testability is not an afterthought for you, it is a design decision that happens early, and you see the downstream consequences of every scan chain stitch, every ATPG pattern, every timing constraint you write. When something does not simulate cleanly, you dig in, trace it back, and figure out what actually went wrong.

Working across teams comes naturally. Design hands you an RTL block, implementation gives you a floorplan, and you figure out how to make it testable without breaking timing or blowing up area. You do not need perfect documentation to get started. You ask the right questions, align on what matters, and move forward even when the spec is still being written. Mentorship matters to you, whether you are learning from someone with more context or helping a newer engineer understand why their coverage numbers look wrong. At Synopsys, you will work on IP cores and SoC integration projects that power real products.

What You'll Be Doing

Own end-to-end DFT implementation including scan chain insertion, stitching, ATPG pattern generation, and fault simulation
Develop and validate timing constraints for mission mode and DFT test modes to ensure coverage without compromising performance
Collaborate with RTL design and physical implementation teams to integrate DFT structures early and avoid late-stage design churn
Support customer engagements during IP integration and silicon bring-up, troubleshooting test failures and refining coverage strategies
Automate repetitive DFT workflows using Perl, TCL, or Python to improve turnaround time and reduce manual error
Debug complex scan and ATPG issues across large multi-million gate designs using simulation and synthesis tools
Mentor junior engineers on DFT fundamentals, tool usage, and best practices in testability design

The Impact You Will Have

Improve test coverage and fault detection rates across Synopsys IP portfolios, directly reducing silicon risk for customers
Accelerate time-to-market by delivering clean, testable IP blocks that integrate smoothly into customer SoCs
Enable seamless silicon bring-up by providing robust test infrastructure that catches manufacturing defects early
Establish and refine DFT methodologies that scale across multiple product lines and geographies
Reduce customer support load by delivering IP with proven test readiness and clear integration documentation
Build team capability by sharing knowledge, reviewing designs, and helping newer engineers develop strong DFT instincts

What You'll Need

Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or related field
5+ years of hands-on DFT experience in scan insertion, ATPG, JTAG, MBIST, and fault simulation
Proficiency with Synopsys DFT tools such as Design Compiler, DFTMAX, TetraMAX, and VCS
Strong scripting skills in Perl, TCL, or Python for automating DFT flows and post-processing results
Experience debugging timing violations, coverage gaps, and simulation mismatches in complex multi-clock domain designs
Exposure to customer-facing roles or IP integration projects is a plus

Who You Are

You approach problems methodically, breaking down complex test failures into root causes rather than guessing at fixes
You communicate clearly across disciplines, translating DFT requirements into language that makes sense to designers, layout engineers, and customers
You are detail-oriented without losing sight of the bigger picture, knowing when a coverage gap is critical and when it is acceptable risk
You take ownership of your work end to end, from initial scan insertion through post-silicon debug
You value collaboration and knowledge sharing, whether reviewing a colleague's constraints file or walking a new hire through their first ATPG run

The Team You'll Be Part Of

You will join a skilled DFT engineering team that values collaboration, technical rigor, and continuous learning. The team works across multiple IP product lines and supports customer engagements globally. You will have access to mentorship from senior engineers and the opportunity to shape DFT methodologies that impact Synopsys products worldwide.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Apply Now

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