Gujarat Design verification engineer Jobs – 96 Open Jobs Today

Senior Formal Verification Engineer
TechBiz Global GmbH —Ahmedabad, Gujarat
- Full-time
- Remote
- Doctoral degree
- B.Sc
- Master's degree
Quick apply
Firmware Engineer
TechBiz Global GmbH —Ahmedabad, Gujarat
- Full-time
- Hybrid work
- Analysis skills
- C++
- Bachelor's degree
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Testing Lead
Sunshine Workforce Solutions —Vadodara, Gujarat
- Full-time
- Leadership
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Deputy General Manager/General Manager (Corporate Project Safety)
Gujarat Fluorochemicals —Vadodara, Gujarat
- Project management
- Electrical experience
- Bachelor's degree
Analytical Development Scientist I
Bayer —Vapi, Gujarat
- Call employer
- Master's degree
- AI
- Communication skills
1d
Technical Project Manager
Rlogical Techsoft —Ahmedabad, Gujarat
- Email
- B.Sc
- Master's degree
- Project management
Manager - Medical Device Quality & Regulatory Documentation
DASH TECHNOLOGIES INC —Ahmedabad, Gujarat
- Azure
- Engineering
- Bachelor's degree
Quick apply
1d
Project Documentation Engineer - Pharma
GEA Group Aktiengesellschaft —Vadodara, Gujarat
- Full-time
- Project management
- Bachelor's degree
- Travel
13d
Engineer - Validation and Testing
GEA Group Aktiengesellschaft —Vadodara, Gujarat
- Full-time
- Project management
- Bachelor's degree
- Travel
13d
Business Analyst
HOPS Healthcare —Ahmedabad, Gujarat
- Full-time
- Microsoft Outlook
- Computer Science
- Microsoft Office
Sr. QA Automation Engineer
WebLineIndia —Ahmedabad, Gujarat
- Full-time
- Remote
- Computer Science
- Software troubleshooting
- Java
- Paid time off
- Work from home
Senior Embedded Audio Engineer (Ahmedabad/ Pune)
Alten Calsoft Labs —Unknown, Gujarat
- Full-time
- Software development
- Linux
- Communication skills
Quick apply
Principal Engineer_Technology Development
Tata Electronics —Ahmedabad, Gujarat
- Doctoral degree
- Engineering
- Master's degree
8d
Senior Embedded Software Engineer
Qualitrol —Ahmedabad, Gujarat
- Software troubleshooting
- DevOps
- Java
QA/QC Manager – PMC (Power Transmission, Substation & Renewable Integration)
AECOM —Gandhinagar, Gujarat
- Full-time
- Microsoft Powerpoint
- AutoCAD
- Microsoft Excel
- Health insurance
- Paid time off
FPGA Engineer
A&W Engineering Works —Vadodara, Gujarat
QA Engineer
Centre for Computational Technologies —Ahmedabad, Gujarat
- Azure
- Oracle
- DevOps
Sr. Supplier Quality Manager
GE Vernova —Vadodara, Gujarat
- Full-time
- Up to 50% travel
- Engineering
- English
HVDC/ VSC System Expert- Substation/HVDC
AECOM —Olpad, Gujarat
- Full-time
- Master's degree
- Electrical experience
- Bachelor's degree
- Health insurance
- Paid time off
QA Manager
Genea Energy Partners —Ahmedabad, Gujarat
- Analysis skills
- JavaScript
- APIs
- Health insurance
- Paid time off

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Senior Formal Verification Engineer

TechBiz Global GmbH
Ahmedabad, Gujarat

Quick apply

Job details

Full-time

Qualifications

Doctoral degree
B.Sc
Master's degree
Bash (Unix shell)
Bachelor's degree
M.Sc
Computer Engineering
Scripting
SystemVerilog
Electrical Engineering
Python
Design patterns

Full job description

At TechBiz Global, we are providing recruitment service to our TOP clients from our portfolio. We are currently seeking a Senior Formal Verification (FV) Engineer to join one of our clients' teams.

Reporting directly to the Vector Unit Verification Lead, this is a highly technical Individual Contributor (IC) role. In this position, you will be the dedicated formal expert for the VU team, responsible for designing scalable formal testbenches, writing mathematical properties, and ensuring the absolute algorithmic and architectural integrity of our vector pipeline. You will work side-by-side with VU microarchitects to hunt down deep corner-case bugs and achieve formal sign-off on high-complexity arithmetic and execution blocks.

Key Responsibilities

Block-Level Execution & Convergence Engineering (90%)

End-to-End Testbench Ownership: Design, deploy, and maintain robust formal verification environments for complex Vector Unit sub-blocks (e.g., Vector Execution Pipelines, Vector Register File/Rename interfaces, and Vector Floating-Point Units).
Datapath & Arithmetic Verification: Implement advanced word-level modeling, bit-blasting, and algebraic rewriting strategies to verify complex IEEE-754 floating-point and integer vector arithmetic units.
Proof Convergence Management: Independently diagnose and resolve proof-convergence failures, over-constraints, and state-space explosions using advanced reduction techniques (e.g., case-splitting, black-boxing, and abstraction modeling).
RISC-V Vector Compliance: Develop formal environments to mathematically prove that the VU pipeline strictly complies with the RISC-V Vector (V) Extension specification.
Simulation Partnership: Collaborate closely with VU simulation engineers to define a razor-sharp boundary between simulation and formal verification, ensuring maximum bug-hunting efficiency and zero coverage gaps.

Embedded Mentorship & Best Practices (10%)

Formal-Friendly Design: Partner with VU microarchitects during early-stage RTL development to drive formal-friendly coding styles and structural design patterns.
SVA Propagation: Review and refine SystemVerilog Assertions (SVA) written by design and simulation peers, establishing best practices for block-level assertions within the VU team.

Education: B.S./M.S. in Computer Engineering, Electrical Engineering, or Computer Science with practical industry execution; or a Ph.D. with a research focus on formal methods or computer arithmetic.
Experience: 5+ years of production-grade hardware verification experience (or Ph.D. + 1–3 years) with a strong, proven track record of applying formal verification to CPU, GPU, or DSP execution pipelines.
Collaboration Style: A self-driven engineer who enjoys deep mathematical puzzles, collaborates seamlessly within a localized block-level team, and can translate complex proof counter-examples into actionable bugs for designers.
Datapath Validation Focus: Strong specialization in arithmetic formal verification, algebraic rewriting, and word-level modeling. Familiarity with control-path formal techniques (liveness, safety properties) is highly welcome.
Vector Microarchitecture: Good working knowledge of high-width execution pipelines, vector execution units, or floating-point/integer arithmetic hardware. Experience with Out-of-Order execution mechanics is a plus.
Formal Tools: Proficient command of commercial EDA formal tools (e.g., Cadence JasperGold/DPV, Synopsys VC Formal, Siemens OneSpin) and their specialized mathematical/datapath apps.
Languages: Native fluency in SystemVerilog and SystemVerilog Assertions (SVA). Scripting proficiency (Python, Tcl, or Bash) for testbench automation.

Nice to Have

RISC-V Core Verification.
RISC-V Ecosystem: Familiarity with the RISC-V Architecture, specifically the Vector (V) and Floating-Point (F/D) extension ecosystems.
Emulation platforms (Veloce, ZeBu).
Core/Bus interface protocols (e.g., AXI/CHI).

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Refine Your Search

design verification engineer jobs in gujarat

Senior Formal Verification Engineer

Firmware Engineer

Testing Lead

Deputy General Manager/General Manager (Corporate Project Safety)

Analytical Development Scientist I

Technical Project Manager

Manager - Medical Device Quality & Regulatory Documentation

Project Documentation Engineer - Pharma

Engineer - Validation and Testing

Business Analyst

Sr. QA Automation Engineer

Senior Embedded Audio Engineer (Ahmedabad/ Pune)

Principal Engineer_Technology Development

Senior Embedded Software Engineer

QA/QC Manager – PMC (Power Transmission, Substation & Renewable Integration)

FPGA Engineer

QA Engineer

Sr. Supplier Quality Manager

HVDC/ VSC System Expert- Substation/HVDC

QA Manager

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