Date posted 05/27/2026
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You have spent years deep in the details of digital IC design, and you know that the difference between a chip that works and one that doesn't often comes down to decisions made during DFT planning. You are the engineer who catches those decisions early, who can look at a scan architecture and immediately see where the coverage gaps will show up three months later during silicon bring-up. You have debugged enough ATPG failures and MBIST issues to know that the best solutions start with understanding what the customer is actually trying to build, not just what they think they need.
You operate at the intersection of deep technical work and customer collaboration. You can spend the morning implementing a complex test access network for a multi-IP SoC and the afternoon explaining to a customer why their current flow is leaving test coverage on the table, and you are equally comfortable in both modes. You do not wait for perfect specs. You ask the right questions, prototype quickly, and iterate based on what you learn.
At Synopsys, you will work with customers designing some of the most complex chips in automotive, AI, and consumer electronics, and what you deliver will directly determine whether their silicon works on the first spin.
-
Deliver end-to-end DFT solutions for customer designs, from architecture planning and scan insertion through pattern generation, silicon bring-up, and diagnostics analysis
-
Implement and validate test solutions including scan, MBIST, and IEEE 1687 architectures for complex SoCs with multiple IP blocks
-
Participate in customer design reviews to understand their flows, identify gaps, and propose specific improvements that reduce test time or increase coverage
-
Prototype and validate new DFT methodologies in collaboration with Solution Architects, proving out viability before customer deployment
-
Provide technical support and training to customers, including hands-on problem resolution, methodology workshops, and account-level engagement
-
Conduct product demonstrations, competitive benchmarking, and evaluations to help win new customers and expand adoption of Synopsys test solutions
-
Analyze silicon test data, diagnose failures, and present findings to both internal teams and customer stakeholders with clear recommendations
-
Enable first-time silicon success for customers by delivering robust, validated DFT solutions that catch issues before tapeout
-
Accelerate time-to-market for automotive and consumer electronics customers by optimizing their test flows and reducing pattern generation cycles
-
Expand Synopsys' footprint in next-generation test technologies by proving out new methodologies that become standard practice across accounts
-
Build long-term customer relationships that turn one-time engagements into strategic partnerships, increasing account value and retention
-
Raise the technical capability of customer teams through training and knowledge transfer, creating a multiplier effect beyond individual projects
-
Shape the direction of Synopsys test products by feeding real-world customer challenges and use cases back to R&D teams
-
Contribute to measurable improvements in test coverage, pattern count reduction, and silicon yield across diverse customer programs
-
Bachelor's degree with 7+ years or Master's degree with 5+ years in Electronics Engineering, Electrical Engineering, Computer Engineering, or related field
-
Hands-on experience with RTL coding, DFT insertion, ATPG pattern generation, and silicon bring-up for digital ICs
-
Deep knowledge of scan architectures, fault models, test access networks, and IEEE standards including 1149.1, 1500, and 1687
-
Proven ability to handle scan implementation and validation for large, multi-IP SoCs with complex hierarchies and multiple clock domains
-
Experience with MBIST concepts, architecture planning, and integration in automotive or safety-critical design environments is a strong plus
-
Familiarity with industry-standard DFT tools and flows, exposure to Synopsys TetraMAX, DFT Compiler, or MBIST Architect is valuable
-
Strong written and verbal communication skills to translate technical concepts for both engineering teams and non-technical stakeholders
-
You can walk into a customer design review, absorb their methodology in real time, and walk out with three specific recommendations they can act on next week
-
You are comfortable working independently on complex technical problems while knowing when to pull in a Solution Architect or R&D engineer for a second opinion
-
You manage multiple customer engagements at once without dropping threads, keeping track of where each project stands and what needs to happen next
-
You prototype quickly and iterate based on feedback, treating customer pushback as useful signal rather than friction
-
You explain tradeoffs clearly, whether you are talking to a junior engineer learning DFT or a VP trying to understand why test time matters for their product schedule
-
You stay current on emerging test standards and methodologies because you are genuinely curious about where the technology is headed, not just what you need to know today
Your recruiter will
