Date posted 06/15/2026
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You have spent over a decade building digital designs that ship in real products, not just pass verification. The kind of work where a timing closure mistake or a protocol misinterpretation costs months, and you have learned to catch those issues before they become problems. You think in micro-architectures, not just RTL. When you read a functional spec, you see the tradeoffs between area, power, and performance before you write a single line of SystemVerilog.
Die-to-die communication protocols like UCIe, PCIe, or DDR are not buzzwords to you. They are systems you have implemented, debugged at 2am, and optimized until they met both the spec and the silicon constraints. You know the difference between a design that works in simulation and one that closes timing at 28nm with real P&R constraints.
Leading a team does not mean delegating tasks. It means sitting with a junior engineer to debug a CDC violation, pushing back when a customer requirement does not make technical sense, and making sure your team understands why a decision was made, not just what to code. You are comfortable working across Noida, Bangalore, and San Jose time zones without losing context or momentum.
At Synopsys, you will architect IP cores that power the next wave of automotive and consumer chips, and the designs you own will matter.
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Architect and implement RTL designs for high-performance IP cores focused on die-to-die communication protocols including UCIe, targeting consumer and automotive applications
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Write micro-architecture documents that translate functional specifications into implementable design solutions for complex digital components, defining data paths, control logic, and interface behavior
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Own the full design flow from RTL coding in SystemVerilog through synthesis, CDC analysis, formal verification, and static timing closure using tools like Fusion Compiler
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Collaborate directly with the verification team to define testplans, close coverage gaps, and debug corner cases that surface during regression or customer testing
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Interface with customers to clarify specification ambiguities, align on design intent, and ensure the IP meets real-world integration requirements
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Mentor a distributed team of ASIC designers across multiple sites, reviewing code, guiding architecture decisions, and building technical depth in protocols and design methodology
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Drive quality processes including revision control with Perforce, scripting automation in Perl or Shell, and adherence to IP design standards for reuse and scalability
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Deliver production-ready IP cores that enable high-speed, low-latency die-to-die communication in next-generation automotive and consumer SoCs shipping to millions of devices
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Define architectural approaches for UCIe and related protocols that position Synopsys as a technical leader in chiplet and multi-die integration markets
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Reduce customer integration risk and time-to-market by delivering IP that meets timing, power, and area targets out of the box with minimal rework
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Elevate team capability across Noida and global sites by mentoring engineers on advanced RTL techniques, synthesis strategies, and protocol implementation best practices
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Influence product roadmaps and feature prioritization by providing technical feedback grounded in real silicon constraints and customer deployment scenarios
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Strengthen Synopsys IP quality reputation through rigorous design practices, comprehensive documentation, and proactive collaboration with verification and physical design teams
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Accelerate adoption of new design flows and tools like P&R-aware synthesis by piloting techniques and sharing learnings across the broader engineering organization
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BSEE or MSEE in Electrical Engineering with 12+ years of hands-on experience in ASIC digital design and RTL implementation
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Deep expertise in at least one of the following protocols: UCIe, Ethernet, DDR, PCIe, CXL, or USB, with proven experience taking designs from architecture through silicon or customer delivery
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Strong command of micro-architecture definition, RTL coding in Verilog and SystemVerilog, and ASIC design flows including synthesis, CDC analysis, formal checking, and static timing analysis
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Hands-on experience with high-speed design considerations, P&R-aware synthesis techniques, and advanced EDA tools such as Fusion Compiler or equivalent
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Proficiency with revision control systems like Perforce and scripting languages such as Perl or Shell for automation and flow development
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Demonstrated experience technically leading and mentoring a team of ASIC designers, including code reviews, architecture guidance, and skill development
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Familiarity with IP design quality processes, reuse methodologies, and verification collaboration in multi-site or customer-facing contexts is a strong plus
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You can sit in a specification review, spot a gap or ambiguity that will cause problems three months later, and raise it in the moment without waiting for formal sign-off
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You write RTL that other engineers can read, modify, and reuse six months later without needing you in the room to explain what you were thinking
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When a design does not close timing, you do not just tweak constraints. You go back to the micro-architecture, understand the critical path, and propose a solution that fixes the root cause
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You are comfortable explaining a complex protocol tradeoff to a customer in two sentences, then turning around and walking a junior engineer through the same decision with enough detail that they learn the reasoning, not just the answer
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You treat mentorship as part of the job, not an extra task. You make time to review code, answer questions, and help your team get better at what they do
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You work across time zones and sites without losing context, and you know how to keep a distributed team aligned on architecture decisions and design intent
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