Mohan Nagar Ghaziabad Uttar Pradesh It recruiter work from Jobs – 134 Open Jobs Today

Memory Layout Design Engineer, Staff
Synopsys —Noida, Uttar Pradesh
- Master's degree
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IPS-Integrated Project Services —Naraina, Delhi, Delhi
- Full-time
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- English
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- Hybrid work
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ASIC Digital Design, Principal Engineer
Synopsys —Noida, Uttar Pradesh
- Electrical experience
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- In-person
R&D Engineering, Staff Engineer (Design Verification/ VIP Verification Engineers)
Synopsys —Noida, Uttar Pradesh
- Computer Science
- Master's degree
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Layout Design, Sr Staff Engineer
Synopsys —Noida, Uttar Pradesh
- Master's degree
- Bachelor's degree
- Scripting
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Mott MacDonald —Noida, Uttar Pradesh
- Full-time
- AutoCAD
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13d
Building Physics Engineer
Mott MacDonald —Noida, Uttar Pradesh
- Full-time
- Engineering
- Bachelor's degree
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Senior BIM Technician - Bridges
WSP —Noida, Uttar Pradesh
- Hybrid work
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Analog Design, Sr Engineer
Synopsys —Noida, Uttar Pradesh
- Master's degree
- Bachelor's degree
- Electrical Engineering
- Health insurance
8d
Senior Mechanical Engineer(PHE)
Mott MacDonald —Noida, Uttar Pradesh
- Full-time
- AutoCAD
- B.Sc
- Bachelor's degree
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Analog Design, Sr Staff Engineer
Synopsys —Noida, Uttar Pradesh
- Doctoral degree
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Principal Mechanical Engineer
Mott MacDonald —Noida, Uttar Pradesh
- Full-time
- B.Sc
- Bachelor's degree
- HVAC
- Health insurance
- Paid sick time
Senior Electrical Engineer
Mott MacDonald —Noida, Uttar Pradesh
- Full-time
- Agile
- Health insurance
Mechanical Engineer
IPS-Integrated Project Services —Naraina, Delhi, Delhi
- Full-time
- Bachelor's degree
- Agile
Architect Designer
IPS-Integrated Project Services —Naraina, Delhi, Delhi
- Full-time
- AutoCAD
- Agile
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Mechanical Designer
IPS-Integrated Project Services —Naraina, Delhi, Delhi
- Full-time
- AutoCAD
- Agile
Engineer Mechanical - Pumping Station
WSP —Noida, Uttar Pradesh
- Hybrid work
- B.Sc
- Master's degree
- Bachelor's degree

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Memory Layout Design Engineer, Staff

Synopsys -
Noida, Uttar Pradesh

Apply Now

Job details

Qualifications

Node.js
Master's degree
Bachelor's degree
Perl
Scripting
AI
Python

Full job description

Date posted 07/13/2026

Category Engineering Hire Type Employee Job ID 17875 Remote Eligible No Date Posted 07/13/2026

Memory Layout Design Engineer, Staff

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years deep in the details of custom memory layout, and you know that the difference between a memory compiler that ships and one that stalls out is usually in how you handled density, matching, and DRC closure three weeks before tape-out. You think in layers, in device symmetry, in parasitic trade-offs. When a circuit designer hands you a schematic, you see not just what they drew but what they meant, and you know how to translate that intent into a layout that works across process corners and actually manufactures.

You do not wait for someone to tell you the DRC is broken. You catch it, you debug it, and you drive the fix. You have migrated designs across technology nodes and lived through the surprises that come with FinFET scaling. You can sit with a junior engineer and explain why their routing choice will create an antenna violation, and you can sit with a methodology team and push back when an automation script does not account for real layout constraints.

At Synopsys, you will work on memory IP that powers chips across the industry. The work is technical, the problems are real, and what you design will ship.

What You'll Be Doing

Design and own custom layouts for SRAM, Register Files, ROM, and related memory compiler IP blocks from floorplan through final signoff
Execute and close DRC, LVS, ERC, antenna, density, and reliability checks using Virtuoso and physical verification tools
Drive technology node migrations for memory compilers, resolving layout and verification issues that emerge with new process rules
Collaborate directly with circuit designers to ensure schematic-layout correlation, device matching, symmetry, and design intent are preserved
Develop and refine layout methodologies, automation scripts in Tcl, Perl, or Python, and best practices that improve team efficiency and design quality
Review layouts created by junior engineers, provide technical guidance, and mentor on complex layout challenges
Support customer-specific memory customization projects, working through optimization requests and delivering production-ready IP

The Impact You Will Have

Your layouts will directly enable memory IP that ships in high-volume semiconductor products across automotive, mobile, AI, and data center applications
You will reduce design cycle time by improving layout automation and methodology, allowing the team to take on more projects with higher quality
Your ability to close complex DRC and LVS issues independently will unblock project milestones and keep compiler development on schedule
You will raise the technical bar for the team by mentoring junior designers and establishing layout standards that scale across technology nodes
Your collaboration with circuit and CAD teams will surface layout-driven insights that influence architecture and tool development decisions
You will help Synopsys deliver memory IP that meets the most demanding area, performance, power, and reliability requirements from leading semiconductor companies
Your work on technology migrations will position the memory IP portfolio for next-generation nodes and maintain Synopsys leadership in the market

What You'll Need

Bachelor's or Master's degree in Electronics, VLSI, Microelectronics, or a related technical field
8 to 10 years of hands-on experience in custom memory layout design, specifically SRAM, Register Files, ROM, or memory compiler development
Strong proficiency with custom layout tools such as Cadence Virtuoso or equivalent platforms
Demonstrated expertise in DRC/LVS closure, device matching and symmetry, and analog/custom layout techniques
Deep understanding of CMOS layout fundamentals, memory architecture, and FinFET technology nodes
Experience with parasitic extraction and physical verification flows, and the ability to interpret and act on results
Familiarity with scripting in Tcl, Perl, or Python for layout automation is a strong plus

Who You Are

You can debug a complex LVS mismatch by tracing through netlists, schematics, and layout views without needing someone to walk you through it
You know when to optimize for area and when to prioritize matching or performance, and you can explain the trade-off to a circuit designer in a way that moves the decision forward
You review a junior engineer's layout and give feedback that is specific, actionable, and grounded in what will actually cause problems downstream
You work across teams with circuit designers, methodology engineers, and CAD without losing sight of what you are trying to deliver or when it needs to be done
You stay current on process technology changes and layout challenges that come with new nodes, and you bring that knowledge into your daily work
You take ownership of your projects and deliver milestones with limited supervision, raising issues early when dependencies or risks emerge

The Team You'll Be Part Of

Your recruiter will

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it recruiter work from jobs in mohan nagar ghaziabad uttar pradesh

Memory Layout Design Engineer, Staff

Architect

Principal Engineer Roads

ASIC Digital Design, Principal Engineer

R&D Engineering, Staff Engineer (Design Verification/ VIP Verification Engineers)

Layout Design, Sr Staff Engineer

Landscape Architect

Building Physics Engineer

Senior BIM Technician - Bridges

Analog Design, Sr Engineer

Senior Mechanical Engineer(PHE)

Analog Design, Sr Staff Engineer

Principal Mechanical Engineer

Senior Electrical Engineer

Mechanical Engineer

Architect Designer

Mechanical Designer

Engineer Mechanical - Pumping Station

I want to receive the latest job alerts for it recruiter work from in mohan nagar ghaziabad uttar pradesh

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Category Engineering Hire Type Employee Job ID 17875 Remote Eligible No Date Posted 07/13/2026

Memory Layout Design Engineer, Staff

We Are

You Are

What You'll Be Doing

The Impact You Will Have

What You'll Need

Who You Are

The Team You'll Be Part Of

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