Customer Requirements & Product Definition
Engage with product and systems teams to thoroughly understand design intent before committing to implementation:
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Study and interpret customer requirements and product definition documents; raise clarifications and track requirement changes
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Translate system-level requirements into block-level technical constraints: gate count budget, clock frequencies, interface bandwidths, and latency targets
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Participate in customer-facing or internal technical reviews to align on scope, schedule, and design assumptions
Architecture & Detailed Design Specification
Define architecture and detailed design specifications based on requirements and evaluated trade-offs:
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Author micro-architecture documents: block diagrams, state machine descriptions, data path sketches, interface signal definitions, and timing budgets
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Evaluate architectural trade-offs: soft IP vs. hard IP, VHDL vs. Verilog coding approach, pipeline depth vs. resource utilization, and clock domain strategies
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Define resource estimates (LUT, FF, BRAM, DSP, SERDES) and present architecture proposals at design review gates
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Document all design decisions and rationale in the engineering design record for traceability through to production
Micro-Architecture & Module Coding
Implement synthesizable RTL for assigned modules across a range of design complexity levels:
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Code production-quality RTL in VHDL and/or Verilog: state machines, data path pipelines, control logic, FIFOs, arbiters, and bus interfaces
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Implement high-speed serial protocol logic covering PCIe Gen5/Gen6, USB 3.2, Ethernet 10G/25G/100G, Aurora, and AMBA-AXI interconnects
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Design digital signal processing blocks: FIR/IIR filters, FFT/IFFT pipelines, decimation/interpolation chains, and fixed-point arithmetic units
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Implement memory interface controllers: DDRx, SRAM, and cache management logic optimized for FPGA memory architecture
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Code peripheral and control interfaces: UART, I2C, SPI, USB, and interrupt controllers with software-accessible register maps
Coding Standards & Design Quality
Maintain RTL coding quality and consistency across all assigned design blocks:
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Apply FPGA-appropriate coding styles: synchronous resets, registered outputs, one-hot FSM encoding, and inference of FPGA primitives (BRAM, DSP, SRL)
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Follow design-for-verification and design-for-implementation guidelines: avoid combinational loops, latches, and uncontrolled clock gating
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Perform self-review and participate in peer design reviews before committing RTL to the design baseline
Multiple Clock Domain Design
Design and implement reliable multi-clock domain architectures:
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Design clock domain crossing (CDC) structures: synchronizers, async FIFOs, handshake protocols, and multi-bit CDC strategies
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Define and document all clock relationships; classify paths as synchronous, asynchronous, or false for constraint authoring
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Use CDC analysis tools (Mentor CDC, Cadence Conformal CDC) to verify crossing structures before synthesis
Testbench Development
Write testbenches for assigned modules achieving complete scenario and corner-case coverage:
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Develop self-checking testbenches in VHDL / SystemVerilog: stimulus generators, response monitors, scoreboards, and coverage collectors
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Write directed tests for nominal operation and constrained-random tests targeting corner cases, protocol violations, and error injection scenarios
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Achieve functional coverage targets: line coverage, branch coverage, FSM state/transition coverage, and toggle coverage prior to sign-off
Simulation & Regression
Execute and manage simulation flows using industry-standard tools:
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Run RTL and gate-level simulations in ModelSim / QuestaSim / Xcelium; analyze waveforms and debug failures to root cause
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Integrate module-level testbenches into team regression suites; triage and resolve failing tests within committed timelines
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Generate and review coverage reports; identify un-exercised scenarios and add targeted tests to close coverage gaps
Protocol & Interface Verification
Verify protocol-level behavior for high-speed interfaces:
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Verify PCIe, USB, Ethernet, AXI, and JESD204B/C interface logic for protocol compliance using BFMs (Bus Functional Models) and VIP
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Validate ADC/DAC interfaces: data capture timing, sample synchronization, and digital front-end alignment
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Document verification results: test coverage matrix, defect log, waiver rationale, and sign-off status per module release
FPGA Implementation Flow
Execute the full FPGA implementation flow from RTL through production bitstream:
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Run synthesis in Xilinx Vivado / PlanAhead and Altera Quartus Prime; analyze utilization, timing, and power reports after each run
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Apply physical constraints: pin assignments, I/O standards, Pblock floorplan constraints, and LOC/BEL directives for performance-critical paths
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Execute place & route iterations targeting timing closure at required frequency and resource utilization within platform budget
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Generate and validate production bitstreams; manage bitstream configuration and partial reconfiguration flows where required
Timing Closure
Own timing closure for assigned partitions based on optimization trade-offs:
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Author SDC/XDC timing constraints: create_clock, set_input_delay, set_output_delay, set_multicycle_path, and set_false_path directives
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Analyze timing reports: identify critical paths, understand slack distribution, and apply RTL or constraint changes to resolve violations
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Apply implementation optimizations: pipeline register insertion, logic replication, carry chain usage, and DSP/BRAM packing for density and speed trade-offs
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Iterate through synthesis strategy sweeps and P&R seed exploration to achieve consistent timing closure across design variants
FPGA Debugging & HW/SW Integration
Debug FPGA designs and support hardware and software integration on target platforms:
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Debug FPGA designs on hardware using Chipscope Pro / Vivado Hardware Manager (Xilinx) and Signal Tap Logic Analyzer (Altera/Intel)
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Use external debug equipment: oscilloscopes, logic analyzers, protocol analyzers, and BERTs to isolate signal integrity and functional failures
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Support HW/SW integration: validate register map access, interrupt routing, DMA data transfers, and driver handshake sequences with embedded software
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Diagnose and resolve hardware failures: capture and analyze waveforms, trace data paths, and identify root cause with systematic debug methodology
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Education: Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related discipline
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Experience: Hands-on FPGA engineering experience including successful completion of at least one FPGA-based product or platform project
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Project Track Record: Must have contributed to a complete FPGA project lifecycle — from RTL coding through implementation and hardware bring-up. Simulation-only or purely academic experience does not qualify.
RTL Design — Must Have
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Coding experience in VHDL and/or Verilog is mandatory — ability to write clean, synthesizable RTL for data path, control, and interface blocks
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Thorough understanding of FPGA-appropriate coding styles: synchronous design, FSM encoding, BRAM/DSP/SRL inference, and registered output disciplines
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Demonstrated understanding of speed vs. density trade-offs and how RTL coding choices directly affect synthesis and P&R quality of results (QoR)
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Experience designing with multiple clock domains: CDC structures, async FIFOs, synchronizers, and clock domain classification for constraints
FPGA Devices & Tools — Must Have
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Experience targeting Xilinx and/or Altera FPGAs is required — familiarity with UltraScale+, Zynq, Versal (Xilinx/AMD) or Agilex, Stratix 10 (Intel/Altera)
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Proficiency with EDA tools: Xilinx Vivado / PlanAhead and/or Altera Quartus Prime for synthesis, P&R, timing analysis, and bitstream generation
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Simulation tool experience: ModelSim, QuestaSim, or equivalent — ability to run regressions, analyze waveforms, and debug simulation failures
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Hardware debug tool proficiency: Chipscope Pro, Vivado Hardware Manager (Xilinx) and/or Signal Tap Logic Analyzer (Altera); familiarity with logic analyzers, oscilloscopes, and protocol analyzers
High-Speed Serial Interfaces — Core
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Practical RTL implementation experience with high-speed serial protocols: PCIe Gen4/5, USB 3.2, Ethernet 10G/25G/100G, or equivalent
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Experience with AMBA-AXI / AXI4-Stream interconnect fabric for on-chip bus integration and DMA data flow
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Familiarity with transceiver / GT architecture: link training, channel bonding, and protocol initialization sequences
Memory & Peripheral Interfaces — Core
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Experience with memory interfaces: DDRx controller integration, timing constraints, and burst access optimization
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Implementation experience with peripheral interfaces: UART, I2C, SPI, or equivalent register-based control interfaces
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Familiarity with ADC/DAC interfaces for data acquisition and signal processing applications
DSP on FPGA — Appreciated
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Experience in RTL implementation of DSP algorithms: FIR/IIR filters, FFT, decimation/interpolation, and fixed-point arithmetic pipelines
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Understanding of DSP slice usage (DSP48E2 / DSP58) for multiply-accumulate, SIMD, and complex multiply operations
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Exposure to radar, communications, or signal processing applications on FPGA is a strong advantage
Advanced Interfaces — Appreciated
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Development experience with PCIe Gen5/Gen6, CXL, 200G/400G Ethernet, or JESD204B/C for high-bandwidth platform designs
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Experience with AMBA APB, AHB, or CHI interconnect protocols for SoC-style FPGA platform architectures
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Familiarity with Vitis AI / Versal DPU for AI/ML inference deployment on FPGA platforms
Technical Ownership
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Proven ability to own assigned RTL modules from specification through verification sign-off and implementation closure with minimal supervision
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Systematic debug mindset: isolates root cause efficiently in both simulation and hardware using structured analysis techniques
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Maintains design documentation, adheres to coding guidelines, and meets design review and coverage gate targets
Execution Excellence
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Delivers RTL blocks, testbenches, and implementation results on committed schedule, flags risks early with proposed mitigations
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Provides accurate effort estimates for RTL tasks, verification scenarios, and timing closure iterations
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Experienced working within structured development milestones: architecture review, RTL freeze, verification sign-off, and implementation release
Collaboration & Communication
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Communicates design decisions, trade-offs, and implementation risks clearly in design reviews and team discussions
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Writes clear technical documentation: module specifications, timing constraint rationale, testbench coverage reports, and hardware debug notes
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Works effectively with hardware, firmware, and software teams during platform integration, bring-up, and validation phases
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Real Design Complexity: Work on multi-million gate FPGA designs with the latest generation protocols — PCIe Gen5/Gen6, 100G+ Ethernet, JESD204B — not reference designs or eval board exercises
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Product Impact: Your RTL ships in defense systems, 5G test platforms, AI accelerators, and robotics platforms used by Tier-1 customers globally
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Full Lifecycle Ownership: Own modules end-to-end — specification, RTL coding, verification, timing closure, and hardware debug. Real accountability at every stage
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Innovation Mandate: Work at the cutting edge of FPGA-AI convergence with Versal AI Core, UltraScale+, and Agilex platforms integrating AI Engines and custom accelerators
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Career Growth: Clear progression from FPGA Engineer to Senior FPGA Engineer and Principal Engineer with structured mentorship from engineers who have shipped multiple complex products
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Equity Upside: Meaningful ESOP allocation in a company transitioning from bootstrapped to VC-backed growth
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Salary commensurate with relevant experience, expertise, and skills.
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Performance Bonus: Annual bonus tied to individual delivery milestones and team OKRs
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Benefits: Health insurance, flexible work options, and paid leaves.
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Equity: ESOP allocation commensurate with seniority and contribution
