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DFT Lead

Ambit Semiconductors -
Hyderabad, Telangana

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Job details

Qualifications

Master's degree
Verilog
Bachelor's degree
Perl
Scripting
SystemVerilog
Communication skills

Full job description

Why Ambit

Are you up for a career that throws challenges and at the same time gives you a sense of pride in what you do? Ambit offers it’s people the ideal platform to toil and grow in the semiconductor design profession. Our people have complete freedom to operate in their own flexible ways and support that help them to learn and enhance their skills further. Ambit firmly believes that for a company to grow big through innovation, its people must be given a free hand to experiment and innovate. The cheerful and bubbly work environment at Ambit portrays the commitment of the management for its people and their values. Come join us today for a bright future in semiconductor design services.

Qualification:

B.Tech / M.Tech or equivalent from a reputed University

Experience:

8- 12 years of relevant experience

Job Description:

Be a member of the team that plays a significant role in ensuring the quality of next generation processors for Smart phones and Smart card through structured DFT, Automatic Test Pattern Generation (ATPG) and Memory Built-In Self-Test (MBIST) techniques. Primary responsibilities will include Interfacing with the design teams to ensure DFT design rules and guidelines are met.
Generating high quality manufacturing ATPG test patterns for (SAF) stuck-at, transition fault (TDF), Path Delay fault (PDF) models and through the use of on-chip test compression techniques. MBIST verification and test pattern generation through Mentor tool.
Work closely with design team on IDDQ constrains validation and pattern generation along with IVA analysis.
Simulating and verifying the ATPG (SAF, TDF) and MBIST patterns on unit delay and min/max timing corners.
Working with the Product/Test engineering teams on the delivery of manufacturing test patterns for ATE debug.
Lead team of 2-3 engineers working bin DFT/ADFT pattern generation and validation
Contribute to technical innovation, development of innovative techniques in the area of test cost reduction, simulation time reduction and quality enhancement
Responsible for supporting post Si debug effort, issue resolution

Skills:

Minimum of 8 -12 year experience in ASIC/DFT and various aspects simulation, Silicon validation
Detailed knowledge on DFT concepts, pattern simulation, Silicon debug
In depth knowledge and hands on experience in ATPG, coverage analysis, Transition delay test coverage analysis.
In-depth knowledge and hands on experience in Silicon debug, yield optimization
Expertise in test mode timing constraints definition, Hands on experience with prime time is an added advantage
Expertise in scripting languages such as perl, shell, etc. is an added advantage
Knowledge/experience in post Si debug support
Experience in simulating test vectors
Working experience in System Verilog, Vera, modelsim tools
Ability to work in an international team, dynamic environment
Ability to learn and adapt to new tools and methodologies.
Ability to do multi-tasking & work on several high priority designs in parallel.
Past experience or ability to manage team
Excellent problem solving skills
Excellent communication and team work skills Experience with test tools such as Tetramax, Logic vision, Modelsim is highly desirable.

Apply Now

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