Date posted 05/19/2026
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You have spent years in the trenches of physical design, taking complex ASICs from netlist to GDSII, and you know that the difference between a chip that tapes out and one that stalls in signoff is usually a decision you made during floorplanning or a timing path you caught in week three. You do not just run tools, you understand what the tools are doing under the hood, and when the flow breaks or the results look wrong, you are the one who digs in and figures out why.
Timing closure does not scare you. Multi-corner multi-mode scenarios, hold violations at 0.85V, IR drop hotspots that appear only in certain power states, these are the puzzles you solve, and you solve them methodically. You have worked across enough nodes and foundries to know that every process has its quirks, and you adapt quickly without needing six months of ramp time.
You care about quality. Clean DRC, passing LVS, EM signoff that actually holds up, these are not checkboxes to you, they are the standard. When you hand off a design, it works. At Synopsys, you will work on foundation IPs and test chips that push the boundaries of what is possible at advanced nodes, and what you build will matter.
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Drive full ASIC physical design implementation from synthesized netlist through floorplanning, placement, CTS, routing, optimization, and final GDSII signoff for complex designs at advanced nodes
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Execute block-level and full-chip PnR flows using industry-standard tools, ensuring designs meet timing, power, and area targets across all operating conditions
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Lead timing closure across multi-corner multi-mode scenarios, resolving setup, hold, and signal integrity violations to achieve signoff-quality results
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Perform parasitic extraction, IR drop analysis, and electromigration checks to ensure power integrity and reliability compliance across all design corners
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Drive physical verification signoff including DRC, LVS, ERC, and foundry-specific checks, resolving violations and ensuring tapeout readiness
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Implement low-power design techniques using UPF/CPF methodologies, managing multi-voltage domains, isolation cells, retention strategies, and power-aware closure
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Build and enhance automation scripts in Shell, Perl, Tcl, or Python to improve flow efficiency, reduce manual effort, and enable repeatable, high-quality results
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Enable successful tapeouts of foundation IPs and test chips that serve as the building blocks for next-generation semiconductor products across multiple foundries
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Accelerate time to signoff by identifying and resolving physical design bottlenecks early, reducing iteration cycles and keeping projects on schedule
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Improve design quality and manufacturability by driving clean physical verification and robust power integrity analysis, reducing risk of silicon respins
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Contribute to early-stage EDA flow adaptation for emerging process nodes, helping Synopsys stay at the forefront of advanced technology adoption
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Establish reusable methodologies and automation that scale across multiple projects, improving team productivity and consistency
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Mentor and guide junior engineers through complex physical design challenges, building technical depth across the team
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Influence foundry engagement and design rule development by providing real-world feedback from advanced node implementations
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Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or related field
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6+ years of hands-on experience in ASIC physical design implementation, with proven track record of taking designs to tapeout
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Deep expertise in physical design flows including floorplanning, power planning, placement, CTS, routing, and optimization using industry-standard tools such as Cadence Innovus, Synopsys ICC2, or similar
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Strong proficiency in Static Timing Analysis using tools like PrimeTime or Tempus, with demonstrated ability to close timing across complex MCMM scenarios
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Solid understanding of physical verification (DRC, LVS, ERC) and signoff methodologies, with hands-on experience using Calibre, ICV, or equivalent tools
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Experience with low-power design implementation using UPF/CPF, including multi-voltage domain management and power-aware closure
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Proficiency in scripting languages such as Tcl, Perl, Python, or Shell for automation and flow development, experience with advanced nodes (7nm and below) is a plus
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You can look at a floorplan and immediately spot the congestion hotspot or the clock domain that is going to cause problems three weeks from now
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When a design fails timing by 200ps at a corner you have not seen before, you do not panic, you methodically trace the paths, check the constraints, and figure out what is actually broken
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You write scripts that other engineers can actually use, with clear logic, helpful comments, and error handling that catches problems before they cascade
You communicate trade-offs clearly, whether you are explaining to a design lead why moving a block will cost two days but- a week in routing, or walking a verification engineer through an LVS debug
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You stay current on what is changing in advanced nodes, new design rules, new foundry requirements, new tool capabilities, and you adapt your approach accordingly
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You take ownership of what you build, if something you delivered causes a problem downstream, you are the first one to jump in and fix it
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