Faridabad Haryana Director of engineering Jobs – 112 Open Jobs Today

Solution Director
HCLTech —Noida, Uttar Pradesh
- Master's degree
- Analysis skills
- Bachelor's degree
1h
Solutions Director
HCLTech —Gautam Budh Nagar, Uttar Pradesh
- Azure
- Computer Science
- Master's degree
Project Manager
Pipecare Group —Noida, Uttar Pradesh
- Full-time
- Microsoft Word
- Microsoft Excel
- Microsoft Outlook
Customer Relationship Management (Export)
Dhruv Enterprises —Faridabad, Haryana
- ₹58,000 - ₹60,000 a month
- Urgently hiring
- Microsoft Excel
- ERP systems
- English
- Flexible schedule
Quick apply
Delivery Manager
Rightsline Inc —Noida, Uttar Pradesh
- Full-time
- Hybrid work
- Management
- PMP
- Microsoft Office
- Health insurance
- Flexible schedule
Quick apply
CAD Verification Director
Qualcomm —Noida, Uttar Pradesh
- Doctoral degree
- Computer Science
- CAD
7d
Associate Director - Applied AI and Analytics
EY —Gurugram, Haryana
- Azure
- DevOps
- Research
22h
Director - Quality HIM
CorroHealth Inc —Noida, Uttar Pradesh
- Full-time
- Master's degree
- Bachelor's degree
- Business Administration
Quick apply
Procurement Engineer – Fire Protection Systems
AGNIM ENGINEERZ PVT. LTD —Noida, Uttar Pradesh
- ₹33,000 - ₹42,000 a month
- Full-time
- Microsoft Excel
- System design
- Bachelor's degree
- Paid time off
Quick apply
8d
Project Manager
Stars and Merit Constructions & Engineering Pvt. Ltd. —Sultanpur, Delhi, Delhi
- ₹50,000 - ₹90,000 a month
- Full-time
- AutoCAD
- PMP
- Project management
Quick apply
Publication Co-Ordinator (Managerial Position)
MBA Journals —Noida, Uttar Pradesh
- Master's degree
- MBA
Asst. Director - NADDSO
Council for Robotics & Automation (AICRA) —Jasola, Delhi, Delhi
- ₹40,000 - ₹60,000 a month
- Master's degree
- Business development
- Bachelor's degree
Professor with Administrative Responsibility
Sharda University —Greater Noida, Uttar Pradesh
- Doctoral degree
- Computer Science
- Master's degree
Claude Solution Architect
EXL Service —Noida, Uttar Pradesh
- Full-time
- Azure
- Computer Science
- Master's degree
Associate – Structures (Substations)
WSP —Noida, Uttar Pradesh
- Hybrid work
- Microsoft Word
- Microsoft Excel
- Microsoft Outlook
Director- Architect
apexanalytix —Noida, Uttar Pradesh
- Full-time
- Computer Science
- Bachelor's degree
- Travel
Quick apply
5d
TC - CS - Data Protection and Privacy - AD
EY —Noida, Uttar Pradesh
- AWS
- Recruiting
- AI
- Health insurance
10d
Manager - Nasscom Insights
Nasscom —Noida, Uttar Pradesh
- Public speaking
- Research
- Microsoft Office
Quality Assurance Head
Diksha Elite Academy —Greater Noida, Uttar Pradesh
- ₹10,00,000 - ₹12,00,000 a year
- Full-time
- English
- Bachelor's degree
- In-person
Quick apply
Assistant Director- Pricing
EY —Gurugram, Haryana
- Microsoft Excel
- English
- Research

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Solution Director

HCLTech -
Noida, Uttar Pradesh

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Job details

1 hour ago

Qualifications

Master's degree
Verilog
Analysis skills
SoC
Bachelor's degree
Perl
Scripting
Requirements management
Communications
SystemVerilog
Communication skills
Python
Shell Scripting
Debugging

Full job description

Noida, Uttar Pradesh
Job Summary

Candidates with minimum 20-25 years experience is mandatory

Define ASIC/SoC verification strategy :
Good understanding of ASIC/SoC life cycle

Full chip testplan development:
Has participated in multiple ASIC/SoC verification till tapeout stage

Full chip TB Architecture definition

Experience writing ASIC/SoC testplans

UVM based testbench development

1.Experience in ASIC/SoC Testbench definition

2.Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM)."

SV functional coverage, Assertions coding

1.Expertise & hands-on experience in OVM/UVM methodologies using SV

2.Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans.

C based TB development

1. Experience in developing TB components for SOC with C, SV

Test case development, coding, execution, bug analysis

1. Experience in developing TB components, including functional coverage implementation and assertion coding

2. Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic.

3.Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues.

4. Experience in SOC C based tests coding & debugging

Key Responsibilities

Gate Level Simulation

Experience in Gate level simulation & netlist debugging

Regressions, coverage analysis

Experience in regression failure analysis, Functional and Code Coverage closure

Own and execute verification closure

Experience in Utilizing scripting languages like Perl/Shell scripting to automate regression tests and parse large simulation log files.

Experience in Collaborating closely with the hardware design team to analyze, document, and resolve bug reports efficiently.

Experience in Document test plans, micro-architecture specifications, and verification results for team reviews

Own and lead End-End projects

Experience to lead the micro-architecture and full-chip verification of our next-generation semiconductor products

End-to-end ownership of complex IPs and subsystems, from defining functional specifications to managing final tape-out sign-off. You will architect robust, scalable UVM environments, solve critical architectural bottlenecks, and mentor a team of engineers to ensure first-pass silicon success

Engineering Execution

Develop complex verification components, including bus functional models (BFMs), monitors, predictors, and highly parameterized scoreboards.

Oversee and resolve deep technical issues in Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), linting, and formal verification.

Direct the deployment of advanced verification techniques such as Formal Verification, Hardware Emulation (e.g., Palladium, Zebu), and Power-Aware (UPF/CPF) simulations.

Skill Requirements

Management & Strategy

Act as the primary technical point of contact, interfacing with System Architects, Backend/Physical Design teams, and Post-Silicon Validation teams.

Provide technical mentorship, code reviews, and career guidance to junior and mid-level design and verification engineers.

Establish, standardize, and continuously improve engineering methodologies, automation scripts, and best practices across the organization.

Technical Leadership and Architecture

Experience in defining micro-architecture specifications for high-performance, low-power digital design blocks and subsystems.

Architect advanced, scalable, and reusable constrained-random verification environments from scratch at the SoC and subsystem levels using SystemVerilog and UVM.

Lead the definition of comprehensive design verification (DV) plans, test strategies, and coverage metrics for highly complex SoC features.

Drive critical technical reviews including design specifications, test plans, RTL code quality, and verification completeness.

Other Requirements

EducationDegree:
Bachelor's or Master's degree in Electronics & Communication Engineering (ECE),

Electrical Engineering (EE), VLSI Design, or a closely related field"

Core Technical Skills

Proven industry experience in ASIC/SoC design and verification with multiple successful tape-outs.

Expert Languages: Mastery of SystemVerilog, Verilog, and UVM (Universal Verification Methodology).

Digital Logic: Strong foundational knowledge in digital logic design, finite state machines (FSM), FIFO architectures, and clocking concepts.

Processor Knowledge: Strong understanding of CPU/GPU architectures, cache coherency, and memory controllers (e.g., DDR4/DDR5, HBM) is highly desirable."

Tools: Expert proficiency with industry-leading EDA simulators, debuggers (e.g., Synopsys VCS, Siemens QuestaSim, Cadence Xcelium/Verd), and emulation platforms.

Protocols: Deep, authoritative knowledge of high-speed protocols (e.g., SPI, I2C,PCIe, NVMe, Ethernet, USB) or complex bus architectures (e.g., AMBA AXI/CHI/ACE)."

Scripting: Advanced capability in Python, Tcl, or Perl to create custom automation infrastructure for regressions and metrics tracking.

Soft Skills

Strategic Thinking: Ability to foresee technical risks weeks or months in advance and proactively implement mitigation strategies.

Influence: Strong leadership and communication skills to guide cross-functional teams and align stakeholders on technical directions.

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director of engineering jobs in faridabad haryana

Solution Director

Solutions Director

Project Manager

Customer Relationship Management (Export)

Delivery Manager

CAD Verification Director

Associate Director - Applied AI and Analytics

Director - Quality HIM

Procurement Engineer – Fire Protection Systems

Project Manager

Publication Co-Ordinator (Managerial Position)

Asst. Director - NADDSO

Professor with Administrative Responsibility

Claude Solution Architect

Associate – Structures (Substations)

Director- Architect

TC - CS - Data Protection and Privacy - AD

Manager - Nasscom Insights

Quality Assurance Head

Assistant Director- Pricing

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