Bengaluru Karnataka Vlsi design verification engineer fresher Jobs – 1 Open Jobs Today

Physical Design Engineer (Trained Intern)
MAXVY —Bengaluru, Karnataka
- Master's degree
- Analysis skills
- Bachelor's degree

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Physical Design Engineer (Trained Intern)

MAXVY
Bengaluru, Karnataka

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Job details

Fresher | Internship

Qualifications

Master's degree
Analysis skills
Bachelor's degree
Scripting
B.E.
Linux
Communication skills
Python
Debugging

Full job description

Location : Bangalore

Experience : Fresher

Education : B.E, M.E, M.Tech, B.Tech

Role :

Key Responsibilities

Perform ASIC physical design tasks from synthesis handoff to GDSII generation.
Execute floor planning, placement, clock tree synthesis (CTS), routing, and physical optimization.
Support timing closure and resolve setup/hold violations.
Perform DRC/LVS checks and assist in physical signoff activities.
Generate and validate GDSII for tape-out.
Work closely with RTL, verification, and DFT teams to achieve implementation goals.
Continuously learn and adopt new tools, methodologies, and process technologies.

Required Skills & Qualifications

Strong understanding of the ASIC Physical Design flow.
Hands-on knowledge of Open ROAD and Open Lane tools, or a strong interest in working with them.
Exposure to one or more semiconductor process technologies or PDKs such as:
- SKY130
- SCL180
- TSMC
- Global Foundries (GF)
project work involving GDSII generation is preferred.
Basic understanding of floor planning, placement, CTS, routing, STA, and physical verification.
Familiarity with Linux and basic scripting (Tcl/Shell/Python) is an advantage.
Excellent analytical and debugging skills.

Preferred Attributes

Self-motivated with a strong willingness to learn independently.
Demonstrated ability to pick up new technologies and solve technical challenges through self-learning.
Good communication and teamwork skills.
Passion for semiconductor design and continuous technical growth.

Job Description :

We are seeking enthusiastic and self-driven Physical Design Engineers who are passionate about VLSI implementation and ASIC design. Candidates should have hands-on exposure to the physical design flow and be eager to work with both open-source and commercial EDA tools.

The ideal candidate should have practical exposure to the complete physical design flow, including floor planning, placement, clock tree synthesis (CTS), routing, timing closure, physical verification, and successful GDSII generation.

The candidate should be capable of working independently as well as collaboratively within a design team.

Salary : Unpaid

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