Engineer asic backend synthesis Jobs

Senior Engineer - ASIC Backend Synthesis
Ericsson —Bengaluru, Karnataka
- Master's degree
- Bachelor's degree
- Scripting
Emulation and FPGA Engineer
NVIDIA —Bengaluru, Karnataka
- Full-time
- B.Sc
- Laboratory experience
- Master's degree
8d
Design Engineer II
Cadence Design Systems —Pune, Maharashtra
- Full-time
- Analysis skills
- Communication skills
- Python
Applications Engineering, Staff Engineer
Synopsys —Bengaluru, Karnataka
- Master's degree
- Electrical experience
- Bachelor's degree
- Health insurance
3d
Sr Engineer - Physical Design & Signoff (Synthesis to GDS2)
Synopsys —Bengaluru, Karnataka
- B.Sc
- Master's degree
- Analysis skills
11d
SoC RTL Design Engineer
Intel —Bengaluru, Karnataka
- Full-time
- Hybrid work
- Computer Science
- Master's degree
- Electrical experience
Principal Engineer- Design
Microchip Technology —Bengaluru, Karnataka
- Full-time
- Master's degree
- Project management
- Bachelor's degree
Sr. Staff Engineer, ASIC Design
Ayar Labs —Bengaluru, Karnataka
- B.Sc
- Master's degree
- C++
- Flexible schedule
Quick apply
Associate II - VLSI
UST —Bengaluru, Karnataka
- Computer Science
- System design
- C++
Quick apply
4d
Staff Engineer, Digital Design Engineering
Analog Devices —Hyderabad, Telangana
- Full-time
- Master's degree
- Analysis skills
- Bachelor's degree
Senior ASIC Design Engineer - XBAR IP
NVIDIA —Bengaluru, Karnataka
- Full-time
- B.Sc
- Master's degree
- Bachelor's degree
Mixed Signal Logic Design Engineer
Intel —Bengaluru, Karnataka
- Full-time
- Hybrid work
- B.Sc
- Master's degree
- Bachelor's degree
Associate III - VLSI
UST —Bengaluru, Karnataka
- Computer Science
- System design
- C++
Quick apply
4d
IP Logic Design Engineer
Intel —Bengaluru, Karnataka
- Full-time
- Hybrid work
- Master's degree
- Analysis skills
- Electrical experience
3d
Principal Engineer Design
Infineon Technologies AG —Bengaluru, Karnataka
- Full-time
- Scripting
- Recruiting
- Software development
3d
ASIC Design Engineer
Axiado —Hyderabad, Telangana
- Full-time
- Python
Quick apply
ASIC Physical Design Senior Manager
Synopsys —Bengaluru, Karnataka
- Walk-in
- Budgeting
- In-person
- Leadership
- Health insurance
Senior ASIC Design Engineer - NOC IP
NVIDIA —Bengaluru, Karnataka
- Full-time
- B.Sc
- Master's degree
- Bachelor's degree
CAD/Methodology Physical Design Team Lead
Cisco Systems —Bengaluru, Karnataka
- Full-time
- B.Sc
- Master's degree
- Bachelor's degree
Staff ASIC Design Engineer
Axiado —Hyderabad, Telangana
- Full-time
- Mentoring
- Communication skills
- Python
Quick apply

I want to receive the latest job alerts for engineer asic backend synthesis

By signing in to your account, you agree to SimplyHired's Terms of Service and consent to our Cookie and Privacy Policy.

Explore jobs in more locations

engineer asic backend synthesis jobs near

Senior Design Engineer jobs in Bengaluru, Karnataka

Senior Design Engineer jobs in Pune, Maharashtra

Principal Software Engineer jobs in Bengaluru, Karnataka

Design Engineer jobs in Bengaluru, Karnataka

Back End Developer jobs in Bengaluru, Karnataka

Senior Staff Engineer jobs in Bengaluru, Karnataka

Digital Designer jobs in Hyderabad, Telangana

Signalling Engineer jobs in Bengaluru, Karnataka

Application Developer jobs in Bengaluru, Karnataka

Design Engineer jobs in Tirunelveli, Tamil Nadu

Senior Design Engineer jobs in Maraimalai Nagar, Chennai, Tamil Nadu

Senior Design Engineer jobs in Bhubaneswar, Orissa

Senior Design Engineer jobs in Faridabad, Haryana

Senior Accountant jobs in Mumbai, Maharashtra

Senior Resident Vacancy, Dental jobs in Delhi

Design Engineer jobs in Aurangabad, Maharashtra

Senior Design Engineer jobs in Chandigarh, Chandigarh

Senior Design Engineer jobs in Chennai, Tamil Nadu

Senior Design Engineer jobs in Baner, Pune, Maharashtra

Senior Chartered Accountant jobs in Mumbai, Maharashtra

Senior Engineer - ASIC Backend Synthesis

Ericsson -
Bengaluru, Karnataka

Apply Now

Job details

Qualifications

5G
R
Electronics Engineering
Slack
Master's degree
Bachelor's degree
M.Sc
Scripting
Agile
Communication skills
Python

Full job description

Grow with us

Join Ericsson’s cutting-edge journey to shape the future of 5G networks! As an Physical Synthesis Engineer, you’ll work on pioneering digital ASIC designs vital to Ericsson’s mobile network infrastructure. Our team, responsible for the final critical stage of chip design before fabrication, thrives on Lean and Agile principles, promoting close collaboration, daily progress-sharing, and continuous improvement. If you’re passionate about advanced technology and ready to make a meaningful impact in telecom, this role is crafted just for you.

At Ericsson, we support your growth, offering opportunities to advance your skills while contributing to game-changing 5G/6G technologies. Here, you’ll find a supportive, innovative environment focused on quality, teamwork, and career development. Join us and help shape the future of telecom!

We are hiring a Physical Synthesis Engineer to own the synthesis flow and constraint development on high-performance, low-power SoC designs. Your primary focus will be physical-aware synthesis, floorplan-driven netlist optimization, and QoR closure — while also contributing to static timing analysis (STA) signoff as well. You will work closely with RTL design, place-and-route, and DFT teams throughout the full design cycle.

What you will do:

Physical-Aware Synthesis (PAS)

Execute physical-aware and floorplan-driven synthesis flows to minimize post-layout timing and congestion surprises.
Integrate synthesis with P&R tools for early physical feedback loops — congestion-aware optimization, placement-aware buffering, and pre-CTS timing.
Collaborate with P&R engineers on DEF/floorplan hand-off; iterate on netlist quality to reduce downstream ECO effort.
Perform flat and hierarchical synthesis for large designs; manage partitioning and interface timing budgets.
Perform formal or equivalence check on the netlist at block or top level.

QoR & Optimization

Track and report key QoR metrics — timing slack, area, cell count, power — across design iterations and process corners.
Identify and resolve synthesis bottlenecks: critical path restructuring, datapath optimization, and register retiming.
Provide RTL coding guideline feedback to design teams to improve synthesizability and QoR from the source.
Manage technology library characterization inputs: Liberty (.lib), LEF, and UPF/CPF for multi-voltage designs.
Own synthesis QoR sign-off checklist and contribute to tape-out readiness reviews.

Static Timing Analysis

Run block-level and full-chip STA using PrimeTime (PT) for timing analysis across PVT corners.
Support MMMC (Multi-Mode Multi-Corner) timing closure; analyze and triage timing violations with P&R and synthesis teams.
Review and validate SDC constraints developed during synthesis against post-layout STA results.
Contribute to clock domain crossing (CDC) checks and timing exception audits during signoff.

The skills you bring:

8+ years in physical synthesis or logic design implementation
Expert-level use of Fusion Compiler
Strong SDC constraint authoring and management skills
Experience with physical-aware synthesis flows and P&R hand-off
Working knowledge of STA (PrimeTime)
Proficiency in Tcl; Python scripting a strong plus
At least one tape-out on 7nm or below

Nice to have:

Familiarity with low-power methodologies (UPF/CPF, multi-Vt, clock gating)
Understanding of PTPX-based power analysis flows
DFT synthesis experience (scan, BIST, boundary scan)
Familiarity with congestion-aware and timing-driven P&R closure

EDA Tools & Environment

Design Compiler, Fusion Compiler, Synopsys PrimeTime, Formality, Tcl/Python.

Education & Background

B.Tech / M.Tech / M.S. in Electronics Engineering, VLSI Design, Computer Engineering, or a related field.
Strong foundation in digital logic design, CMOS circuit theory, and standard-cell library concepts.
Excellent scripting and automation skills; comfort with large, multi-million gate designs.
Strong communication skills — able to clearly present QoR status, risks, and trade-offs to cross-functional teams.

.

“All academic credentials must be from recognized and accredited institutions and are further subject to verification.”

Why join Ericsson?At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.

What happens once you apply?Click Here to find all you need to know about what our typical hiring process looks like.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.

Primary country and city: India (IN) || Bangalore

Req ID: 783577

Apply Now

Refine Your Search

Senior Engineer - ASIC Backend Synthesis

Emulation and FPGA Engineer

Design Engineer II

Applications Engineering, Staff Engineer

Sr Engineer - Physical Design & Signoff (Synthesis to GDS2)

SoC RTL Design Engineer

Principal Engineer- Design

Sr. Staff Engineer, ASIC Design

Associate II - VLSI

Staff Engineer, Digital Design Engineering

Senior ASIC Design Engineer - XBAR IP

Mixed Signal Logic Design Engineer

Associate III - VLSI

IP Logic Design Engineer

Principal Engineer Design

ASIC Design Engineer

ASIC Physical Design Senior Manager

Senior ASIC Design Engineer - NOC IP

CAD/Methodology Physical Design Team Lead

Staff ASIC Design Engineer

I want to receive the latest job alerts for engineer asic backend synthesis

Explore jobs in more locations

Grow with us

What you will do:

The skills you bring:

Nice to have:

Education & Background

.

Jobseeker tools

Employer Tools

Browse

Stay Connected