Ka Vlsi physical Jobs – 92 Open Jobs Today

Associate III - VLSI PD PnR
UST —Bengaluru, Karnataka
Quick apply
PMO-Memory IP Program Manage
Quest Global —Bengaluru, Karnataka
- Full-time
- Hybrid work
- English
- Project management
- Bachelor's degree
Quick apply
Full-Chip Senior Principal Physical Design Engineer
Marvell —Bengaluru, Karnataka
- Full-time
- Master's degree
- Electrical experience
- Bachelor's degree
8d
ASIC front-end verification engineer
Hewlett Packard Enterprise —Bengaluru, Karnataka
- Full-time
- System design
- Scripting
- Agile
Staff Engineer, Physical Design
SiFive —Bengaluru, Karnataka
- Full-time
- Master's degree
- Electrical experience
- Bachelor's degree
Silicon Physical Design STA Lead, Google Cloud
Google —Bengaluru, Karnataka
- Full-time
- Management
- Doctoral degree
- Master's degree
3d
Manager- Physical Design Engineer
THINSIL —HSR Layout, Bengaluru, Karnataka
- ₹40,00,000 - ₹60,00,000 a month
- Full-time
- Management
- Master's degree
- Electrical experience
- Paid time off
- Paid sick time
Quick apply
14d
Full-Chip Principal Physical Design Engineer
Marvell —Bengaluru, Karnataka
- Full-time
- Master's degree
- Electrical experience
- Bachelor's degree
8d
FPGA Architect (CAD & EDA Flows)
Advanced Micro Devices, Inc —Bengaluru, Karnataka
- Doctoral degree
- Computer Science
- CAD
Physical Design Engineer, Google Cloud
Google —Bengaluru, Karnataka
- Full-time
- Doctoral degree
- Scripting
- Electrical Engineering
Engineer I
SiFive —Bengaluru, Karnataka
- Full-time
- Engineering
- Java
- Master's degree
Architect MTS
onsemi —Bengaluru, Karnataka
- Full-time
- Master's degree
- C++
- Bachelor's degree
Senior Physical Design Engineer
Pozibility Technologies —Bengaluru, Karnataka
- Master's degree
- Electrical experience
- Bachelor's degree
ASIC Verification Engineer
Hewlett Packard Enterprise —Bengaluru, Karnataka
- Full-time
- English
- Master's degree
- Analysis skills
1d
ASIC Principal Design Engineer
Hewlett Packard Enterprise —Bengaluru, Karnataka
- Full-time
- Agile
- Electrical Engineering
Senior Engineer - Low Power Design
Ericsson —Bengaluru, Karnataka
- Master's degree
- Bachelor's degree
- Scripting
Lead - Physical Design Engineer
Pozibility Technologies —Bengaluru, Karnataka
- Master's degree
- Electrical experience
- Bachelor's degree
Lead DFT Engineer
Advanced Micro Devices, Inc —Bengaluru, Karnataka
- Master's degree
- Bachelor's degree
- Electrical Engineering
9d
Design and Verification, MTS
onsemi —Bengaluru, Karnataka
- Full-time
- Master's degree
- C++
- Bachelor's degree
Lead Engineer/ Staff – RISCV Subsystem RTL Design
Qualcomm —Bengaluru, Karnataka
- Doctoral degree
- Computer Science
- Master's degree
9d

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Associate III - VLSI PD PnR

UST -
Bengaluru, Karnataka

Quick apply

Job details

Qualifications

Ant
Debugging

Full job description

Role description

Should have led Physical Design execution of low-power, multiple voltage/power domain based SoC
Should be able to handle Die-size estimation, IO/ESD/package planning, Floorplan, power plan
Should be able to drive Synthesis, P&R, timing, Physical Verification and IR/EM convergence

Should be able to handle LP-aware synthesis of SoC, tweak the flow to meet PPA targets
Should be able to debug and resolve RTL2N LEC, N2N, LP-LEC issues
Should be able to run CLP and resolve gate level CLP violations
Familiarity with Multi-voltage, multi-power domain based Low power implementation

Expected to handle constraints bring-up for Func/DFT/IO modes
Should have good constraints debug and validation skills
Should be familiar with timing closure at various stages (preLayout, postLayout)
Familiarity with Multi-voltage, multi-power domain based STA

Should be able to handle P&R of SoC Top
Should be able to customize the PNR flow to meet PPA and low power requirements
Should be able to resolve timing/congestion issues
Should have worked on Multi-voltage, multi-power domain based designs

Should be able to handle power grid development using tool automation and custom scripts
Should have handled SoC level EM/IR analysis (Static, Dynamic IR, power/signal EM) for SoC with power switches
Should be able to analyse, root-cause and fix IRdrop issues

Should be familiar with custom placement/routing using semi-automatic/manual method
Should have worked on Physical Verification checks for Low Power SoC (DRC, ERC, LVS, ANT, ESD, DFM)

Skills

vlsi design,physical design,floorplan,timing analysis,

About UST
UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients’ organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact—touching billions of lives in the process.

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Refine Your Search

vlsi physical jobs in ka

Associate III - VLSI PD PnR

PMO-Memory IP Program Manage

Full-Chip Senior Principal Physical Design Engineer

ASIC front-end verification engineer

Staff Engineer, Physical Design

Silicon Physical Design STA Lead, Google Cloud

Manager- Physical Design Engineer

Full-Chip Principal Physical Design Engineer

FPGA Architect (CAD & EDA Flows)

Physical Design Engineer, Google Cloud

Engineer I

Architect MTS

Senior Physical Design Engineer

ASIC Verification Engineer

ASIC Principal Design Engineer

Senior Engineer - Low Power Design

Lead - Physical Design Engineer

Lead DFT Engineer

Design and Verification, MTS

Lead Engineer/ Staff – RISCV Subsystem RTL Design

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