Up Senior validation engineer Jobs – 117 Open Jobs Today

SOC Engineering, Sr Engineer
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- Master's degree
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- Full-time
- AutoCAD
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- In-person
- Flexible schedule
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NeoXam —Noida, Uttar Pradesh
- Hybrid work
- Java
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- Full-time
- Computer Science
- C++
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Zones —Noida, Uttar Pradesh
- Full-time
- Azure
- Windows
- Scripting
- Health insurance
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Sr Specialist, FEA
Pentair —Noida, Uttar Pradesh
- Full-time
- Doctoral degree
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- Master's degree
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Semarchy xDM Senior Software Development Engineer 1
Sopra Steria —Noida, Uttar Pradesh
- Full-time
- SQL
Quick apply
2d
Senior Test Lead
HCLTech —Noida, Uttar Pradesh
- Project management
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4d
Salesforce QA Engineer
Aigen Technologies —Noida, Uttar Pradesh
- ₹3,00,000 - ₹9,00,000 a year
- Full-time
- Azure
- Salesforce
- DevOps
- Health insurance
- Paid time off
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2d
LiDAR Engineer
CK Aerial Surveys India Pvt Ltd —Vasundhra, Ghaziabad, Uttar Pradesh
- Full-time
- Master's degree
- Bachelor's degree
- In-person
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9d
Senior AI Engineer – (Land Services)
WSP —Noida, Uttar Pradesh
- Hybrid work
- Azure
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- Computer Science
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11d
SOC Engineering, Sr Staff Engineer
Synopsys —Noida, Uttar Pradesh
- Master's degree
- Electrical experience
- Bachelor's degree
- Health insurance
12d
Sr. Principal Design Engineer
Cadence Design Systems —Noida, Uttar Pradesh
- Full-time
- Data analysis skills
- Master's degree
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2d
Design Engineer
Pioneer Machines & Automation (P) Ltd —Ghaziabad, Uttar Pradesh
- ₹25,000 - ₹44,000 a month
- Full-time
- AutoCAD
- CAD
- Math
- Health insurance
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Senior Design Specialist
consultancy service —Noida, Uttar Pradesh
- ₹25,000 - ₹50,000 a month
- Full-time
- AutoCAD
- Master's degree
- Bachelor's degree
Quick apply
Senior Engineer-Ovation Digital Twin (OD Twin)
Emerson —Noida, Uttar Pradesh
- Full-time
- Master's degree
- Electrical experience
- Bachelor's degree
- Health insurance
13d

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SOC Engineering, Sr Engineer

Synopsys -
Noida, Uttar Pradesh

Apply Now

Job details

Benefits

Health insurance

Qualifications

Electronics Engineering
Master's degree
SoC
Bachelor's degree
Perl
Scripting
ARM
SystemVerilog
Debugging

Full job description

Job Title:
SOC Verification - Sr. Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent the last few years deep in verification, and you know the difference between a test plan that looks good in a review and one that actually catches the bugs that matter. You think in layers, from block-level checks to full SOC integration, and you understand that the hardest problems are usually the ones hiding at the boundaries between subsystems.

You are comfortable sitting with a design spec, asking the questions no one else thought to ask, and building a verification strategy that does not just check boxes but actually proves the design works. You do not wait for perfect clarity. You work with architects and designers to fill in the gaps, and you move forward with what you know while staying alert to what you do not.

Debugging energizes you. When a simulation fails at 3 a.m. in a regression run, you are the person who digs into waveforms, traces signals across clock domains, and finds the root cause, not just the symptom. You have written SystemVerilog testbenches, integrated third-party VIPs, and probably cursed at UVM more than once, but you also know it is the right tool for the job.

At Synopsys, you will work on real customer SOCs, not internal demos. The designs are complex, the stakes are high, and what you verify will ship.

What You'll Be Doing

Build verification test plans from design specs for processor-based SOCs, defining scope, coverage goals, and test scenarios that map to real-world use cases
Develop and maintain SystemVerilog testbenches and UVM environments, integrating Synopsys VIPs and third-party verification IP for protocols like AXI, USB, PCIe, and MIPI
Write and analyze SystemVerilog assertions and track code, toggle, and functional coverage to close verification gaps before tapeout
Debug complex simulation failures across multi-clock-domain SOC designs using VCS, waveform viewers, and scripting to isolate root causes
Mentor junior verification engineers through design bring-up, testbench architecture decisions, and debugging sessions
Collaborate with architects, RTL designers, and post-silicon teams to align verification strategy with design intent and silicon validation plans
Script automation flows using shell, Makefile, and Perl to improve regression efficiency and testbench reusability

The Impact You Will Have

Catch critical design bugs before tapeout, reducing costly silicon respins and accelerating time to market for customer products
Deliver verified SOC IP and subsystems that power high-performance computing, automotive, and aerospace applications used by industry leaders and startups alike
Raise the quality bar for verification methodology across the team by introducing best practices, reusable components, and coverage-driven approaches
Enable faster customer success by working directly on service projects that solve real customer SOC challenges using Synopsys EDA tools and IP
Shape the skills and careers of junior engineers through hands-on mentorship, code reviews, and collaborative problem-solving
Drive adoption of advanced verification techniques and Synopsys tooling that improve efficiency and coverage across the Systems Solutions Group
Contribute to SOC designs that end up in products ranging from autonomous vehicles to next-generation data center processors

What You'll Need

Bachelor's or Master's in Electronics Engineering or related field with 2 to 5 years of hands-on experience in IP or SOC verification
Strong working knowledge of SystemVerilog, UVM, and processor-based SOC verification environments
Experience with VCS, waveform debugging tools, and integrating third-party VIPs like Synopsys VIP into testbenches
Solid understanding of AXI and AMBA protocol variants, including how they behave under corner cases and error conditions
Proficiency in scripting with shell, Makefile, or Perl to automate regression flows and post-process simulation results
Working knowledge of ASIC design flow, RTL design concepts, and how verification fits into the broader chip development lifecycle
Experience with ARM core verification, USB, PCIe, or MIPI protocols is a strong plus

Who You Are

You can take a 200-page design spec, identify the five things most likely to break, and build a verification plan around them without being told what to prioritize
When a regression fails on a Friday afternoon, you dig into the waveforms and root-cause the issue instead of punting it to Monday
You explain technical tradeoffs clearly, whether you are talking to a junior engineer who needs guidance or an architect who needs to understand coverage gaps
You write testbenches and assertions that other engineers can actually read, reuse, and extend six months later
Leading a small group through a tough debug session feels natural to you, you ask the right questions, keep the team focused, and make sure everyone learns something
You stay current on verification tools and methodologies because you know the field moves quickly and what worked two years ago might not be the best approach today

The Team You'll Be Part Of

You will join the Systems Solutions Group (SSG), which delivers end-to-end SOC design and verification services to customers tackling the hardest chip problems in the industry. The team works on everything from subsystem blocks to full turnkey SOCs across high-performance computing, automotive, aerospace, and defense. You will collaborate with architects, designers, physical implementation engineers, and Synopsys business unit teams to deploy tool and IP solutions that solve real customer challenges. The work is customer-facing, the designs are complex, and the customers range from startups to industry leaders and government agencies.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Apply Now

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senior validation engineer jobs in up

SOC Engineering, Sr Engineer

Senior Manager - Mechanical and Process Engineer

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Cloud Engineer

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Job Title:
SOC Verification - Sr. Engineer

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Job Title: SOC Verification - Sr. Engineer

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You Are

What You'll Be Doing

The Impact You Will Have

What You'll Need

Who You Are

The Team You'll Be Part Of

Rewards and Benefits

Job Title:
SOC Verification - Sr. Engineer