Gujarat Design verification Jobs – 145 Open Jobs Today

Senior Formal Verification Engineer
TechBiz Global GmbH —Ahmedabad, Gujarat
- Full-time
- Remote
- Doctoral degree
- B.Sc
- Master's degree
Quick apply
Control and Instrumentation Engineer
Larsen & Toubro —Vadodara, Gujarat
- Programmable logic controllers
- Bachelor's degree
2d
Regulatory Compliance Officer
Zymo Cosmetics —Gujarat
- Master's degree
- Bachelor's degree
- Communication skills
HVDC/ VSC System Expert- Substation/HVDC
AECOM —Olpad, Gujarat
- Full-time
- Master's degree
- Electrical experience
- Bachelor's degree
- Health insurance
- Paid time off
Senior Surveyor
LRQA group —Surat, Gujarat
- English
- Microsoft Office
- Bachelor's degree
5d
Senior FPGA Engineer
A&W Engineering Works —Vadodara, Gujarat
- C++
- Scripting
- Python
Deputy General Manager/General Manager (Corporate Project Safety)
Gujarat Fluorochemicals —Vadodara, Gujarat
- Project management
- Electrical experience
- Bachelor's degree
Staff Engineer
SiFive —Ahmedabad, Gujarat
- Full-time
- Master's degree
- Electrical experience
- Bachelor's degree
Firmware Engineer
TechBiz Global GmbH —Ahmedabad, Gujarat
- Full-time
- Hybrid work
- Analysis skills
- C++
- Bachelor's degree
Quick apply
Testing Lead
Sunshine Workforce Solutions —Vadodara, Gujarat
- Full-time
- Leadership
Quick apply
Embedded Firmware Developer
Manektech —Ahmedabad, Gujarat
- Up to ₹8,40,000 a year
- Full-time
- Master's degree
- Analysis skills
- C++
Quick apply
Project Documentation Engineer - Pharma
GEA Group Aktiengesellschaft —Vadodara, Gujarat
- Full-time
- Project management
- Bachelor's degree
- Travel
Principal Engineer_Technology Development
Tata Electronics —Ahmedabad, Gujarat
- Doctoral degree
- Engineering
- Master's degree
11d
Engineer - Validation and Testing
GEA Group Aktiengesellschaft —Vadodara, Gujarat
- Full-time
- Project management
- Bachelor's degree
- Travel
Automation Engineer - Smart Manufacturing
ASSA ABLOY —Jamnagar, Gujarat
- Microsoft Powerpoint
- Microsoft Word
- AutoCAD
Junior Chartered Accountant
VasyERP Solutions —Ahmedabad, Gujarat
- Microsoft Excel
- Microsoft Office
- Accounting
Quick apply
Draftsmen (FMCG) (Contract)
Saaki Argus & Averil Consulting —Vadodara, Gujarat
- AutoCAD
Quick apply
7d
FPGA Engineer
A&W Engineering Works —Vadodara, Gujarat
Engineer/Senior Engineer
Bosch-HomeComfort —Ahmedabad, Gujarat
- Full-time
- Project management
- Bachelor's degree
- Communication skills
Quick apply
Accountant
SDC llp —Surat, Gujarat
- ₹10,000 - ₹20,000 a month
- Full-time
- GAAP
- Accounting
- In-person
Quick apply

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Senior Formal Verification Engineer

TechBiz Global GmbH
Ahmedabad, Gujarat

Quick apply

Job details

Full-time

Qualifications

Doctoral degree
B.Sc
Master's degree
Bash (Unix shell)
Bachelor's degree
M.Sc
Computer Engineering
Scripting
SystemVerilog
Electrical Engineering
Python
Design patterns

Full job description

At TechBiz Global, we are providing recruitment service to our TOP clients from our portfolio. We are currently seeking a Senior Formal Verification (FV) Engineer to join one of our clients' teams.

Reporting directly to the Vector Unit Verification Lead, this is a highly technical Individual Contributor (IC) role. In this position, you will be the dedicated formal expert for the VU team, responsible for designing scalable formal testbenches, writing mathematical properties, and ensuring the absolute algorithmic and architectural integrity of our vector pipeline. You will work side-by-side with VU microarchitects to hunt down deep corner-case bugs and achieve formal sign-off on high-complexity arithmetic and execution blocks.

Key Responsibilities

Block-Level Execution & Convergence Engineering (90%)

End-to-End Testbench Ownership: Design, deploy, and maintain robust formal verification environments for complex Vector Unit sub-blocks (e.g., Vector Execution Pipelines, Vector Register File/Rename interfaces, and Vector Floating-Point Units).
Datapath & Arithmetic Verification: Implement advanced word-level modeling, bit-blasting, and algebraic rewriting strategies to verify complex IEEE-754 floating-point and integer vector arithmetic units.
Proof Convergence Management: Independently diagnose and resolve proof-convergence failures, over-constraints, and state-space explosions using advanced reduction techniques (e.g., case-splitting, black-boxing, and abstraction modeling).
RISC-V Vector Compliance: Develop formal environments to mathematically prove that the VU pipeline strictly complies with the RISC-V Vector (V) Extension specification.
Simulation Partnership: Collaborate closely with VU simulation engineers to define a razor-sharp boundary between simulation and formal verification, ensuring maximum bug-hunting efficiency and zero coverage gaps.

Embedded Mentorship & Best Practices (10%)

Formal-Friendly Design: Partner with VU microarchitects during early-stage RTL development to drive formal-friendly coding styles and structural design patterns.
SVA Propagation: Review and refine SystemVerilog Assertions (SVA) written by design and simulation peers, establishing best practices for block-level assertions within the VU team.

Education: B.S./M.S. in Computer Engineering, Electrical Engineering, or Computer Science with practical industry execution; or a Ph.D. with a research focus on formal methods or computer arithmetic.
Experience: 5+ years of production-grade hardware verification experience (or Ph.D. + 1–3 years) with a strong, proven track record of applying formal verification to CPU, GPU, or DSP execution pipelines.
Collaboration Style: A self-driven engineer who enjoys deep mathematical puzzles, collaborates seamlessly within a localized block-level team, and can translate complex proof counter-examples into actionable bugs for designers.
Datapath Validation Focus: Strong specialization in arithmetic formal verification, algebraic rewriting, and word-level modeling. Familiarity with control-path formal techniques (liveness, safety properties) is highly welcome.
Vector Microarchitecture: Good working knowledge of high-width execution pipelines, vector execution units, or floating-point/integer arithmetic hardware. Experience with Out-of-Order execution mechanics is a plus.
Formal Tools: Proficient command of commercial EDA formal tools (e.g., Cadence JasperGold/DPV, Synopsys VC Formal, Siemens OneSpin) and their specialized mathematical/datapath apps.
Languages: Native fluency in SystemVerilog and SystemVerilog Assertions (SVA). Scripting proficiency (Python, Tcl, or Bash) for testbench automation.

Nice to Have

RISC-V Core Verification.
RISC-V Ecosystem: Familiarity with the RISC-V Architecture, specifically the Vector (V) and Floating-Point (F/D) extension ecosystems.
Emulation platforms (Veloce, ZeBu).
Core/Bus interface protocols (e.g., AXI/CHI).

Quick apply

Refine Your Search

design verification jobs in gujarat

Senior Formal Verification Engineer

Control and Instrumentation Engineer

Regulatory Compliance Officer

HVDC/ VSC System Expert- Substation/HVDC

Senior Surveyor

Senior FPGA Engineer

Deputy General Manager/General Manager (Corporate Project Safety)

Staff Engineer

Firmware Engineer

Testing Lead

Embedded Firmware Developer

Project Documentation Engineer - Pharma

Principal Engineer_Technology Development

Engineer - Validation and Testing

Automation Engineer - Smart Manufacturing

Junior Chartered Accountant

Draftsmen (FMCG) (Contract)

FPGA Engineer

Engineer/Senior Engineer

Accountant

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