Orissa R&d engineer Jobs – 19 Open Jobs Today

R&D Engineering, Staff Engineer
Synopsys —Bhubaneswar, Odisha
- Master's degree
- Bachelor's degree
- In-person
Embedded R&D Engineer
BARIFLO CYBERNETICS PRIVATE LIMITED —Jagatpur, Odisha
- ₹25,000 - ₹35,000 a month
- Full-time
- C++
- Bachelor's degree
- In-person
- Paid time off
- Flexible schedule
Quick apply
Electronics R&D engineer
Velotech innovation private limited —Bhubaneswar, Odisha
- From ₹1,20,000 a year
- Analysis skills
- Bachelor's degree
- In-person
- Cell phone reimbursement
- Paid sick time
Quick apply
Embedded R&D Engineer
VertoX Labs Private Limited —Jagatpur, Odisha
- ₹20,000 - ₹30,000 a month
- Full-time
- C++
- Programmable logic controllers
- Bachelor's degree
- Flexible schedule
- Paid sick time
Quick apply
Production Manager- Advance Material manufacturing/ FPR- Indian Railways
Mounee Consulting Services —Maneswar, Odisha
- ₹50,00,000 a year
- Full-time
- Quality control
- Manufacturing
Quick apply
12d
Chief Technology Officer (CTO) & Co-Founder
BARIFLO CYBERNETICS PRIVATE LIMITED —Cuttack, Odisha
- ₹10,00,000 - ₹12,00,000 a year
- Full-time
- Doctoral degree
- Research
- Master's degree
- Flexible schedule
Quick apply
Embedded R&D Engineer INTERN
BARIFLO CYBERNETICS PRIVATE LIMITED —Bhubaneswar, Odisha
- ₹10,000 - ₹12,000 a month
- Full-time
- Computer Science
- C++
- Electrical experience
- Paid time off
- Flexible schedule
Quick apply
Lead Production Manager
PinnacleU —Maneswar, Odisha
- ₹30,00,000 - ₹32,00,000 a year
- Full-time
- Mentoring
- Manufacturing
Quick apply
Plant Head (Solvent Extraction)
TFarm Pvt Ltd —Koraput, Odisha
- ₹83,333 - ₹1,25,000 a month
- Full-time
- Bachelor's degree
- In-person
- Leadership
- Food provided
Quick apply
Program Manager - Operations, Odisha
Mitti Labs —Odisha
- Remote
- Management
- Sales
- Project management
Quick apply
Principal AI Forward Deployment Engineer
Cadence Design Systems —Odisha
- Full-time
- Doctoral degree
- B.Sc
- Master's degree
Staff DFT Engineer
Synopsys —Bhubaneswar, Odisha
- Master's degree
- Bachelor's degree
- In-person
Production Line Manager - Basic Brick
Calderys —Bhubaneswar, Odisha
- Full-time
- Programmable logic controllers
- Bachelor's degree
- Manufacturing
Production Line Manager - Tap Hole Clay
Calderys —Bhubaneswar, Odisha
- Full-time
- Bachelor's degree
- Manufacturing
- Diploma
Sales Representative I - Surgical Innovation
Medtronic —Bhubaneswar, Odisha
- Full-time
- 12th Pass
- Bachelor's degree
Sales Representative II- Surgical Innovation
Medtronic —Bhubaneswar, Odisha
- Full-time
- 12th Pass
- Bachelor's degree
Sektionschef Assignment Saab Dynamics
Saab —Odisha

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R&D Engineering, Staff Engineer

Synopsys -
Bhubaneswar, Odisha

Apply Now

Job details

Qualifications

Electronics Engineering
Git
Master's degree
Verilog
SoC
Bachelor's degree
Perl
GitHub
SystemVerilog
Electrical Engineering
AI
Python
Debugging
Digital design

Full job description

Date posted 06/29/2026

Category Engineering Hire Type Employee Job ID 17520 Remote Eligible No Date Posted 06/29/2026

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years building RTL that ships in silicon, not just passes simulation. You know that the real work begins when you integrate five IP blocks into a subsystem and discover that three of them assume mutually exclusive clock strategies. You have debugged enough CDC violations at 2 a.m. to know which ones matter and which ones are tool noise, and you can tell the difference in about thirty seconds.

Architecture documents do not intimidate you. You read them, ask the clarifying questions no one else thought to ask, and then build something that actually matches the intent, not just the letter. When synthesis fails at 87% because of a constraint you wrote three weeks ago, you do not panic. You open the log, trace it back, fix it, and move on.

You have written enough SDC to know that constraints are half art, half science, and entirely about understanding what the downstream tools actually need. Glue logic does not scare you. Neither does owning an entire block from microarchitecture through post-synthesis handoff. At Synopsys, you will work on SoC designs that power real products, alongside engineers who care as much about the details as you do.

What You'll Be Doing

Design and develop RTL using Verilog and SystemVerilog for complex SoC and ASIC components that go into production silicon
Integrate IP blocks at the SoC level, building the glue logic and subsystem architecture that makes everything actually work together
Write SDC for synthesis, ensuring your constraints reflect the real timing intent and do not create downstream surprises
Run and debug lint, CDC, and synthesis checks using tools like SpyGlass, Fusion Compiler, and Encounter, resolving issues before they become integration blockers
Collaborate with verification, physical design, and architecture teams to close functional and structural issues across the design cycle
Contribute to microarchitecture discussions and translate architectural intent into working RTL that meets performance, power, and area targets
Mentor junior engineers on RTL quality, coding standards, and front-end design best practices when the opportunity arises

The Impact You Will Have

Your RTL integration work directly enables complex SoCs to move from architecture to physical implementation without costly respins
The synthesis constraints you write determine whether the design meets timing on the first pass or requires weeks of iteration
Your ability to debug CDC and lint issues early prevents verification and physical design teams from hitting walls later in the schedule
The glue logic and subsystem designs you build become the connective tissue that makes multi-IP integration actually function
Your technical guidance helps junior engineers avoid common pitfalls and build higher-quality RTL from the start
The blocks you own and deliver on schedule keep entire project timelines on track
Your collaboration across teams ensures that architectural intent, RTL implementation, and physical constraints stay aligned throughout the design cycle

What You'll Need

Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or a related field with a minimum of 5 years of related experience, or a Master’s degree with 3 years of relevant experience.
Hands-on experience in RTL design and SoC or ASIC integration, with a track record of owning blocks through synthesis
Strong proficiency in Verilog and SystemVerilog for production RTL development
Solid understanding of digital design fundamentals, microarchitecture, and SoC integration challenges
Experience running lint tools like SpyGlass or Leda, CDC analysis tools, and synthesis flows using Fusion Compiler or Encounter
Ability to write SDC and debug synthesis issues in complex, multi-clock designs

Ability to use AI tools (git hub copilot or others)

Experience with high-speed interfaces like PCIe, USB, AXI, I2C, or JTAG is a strong plus, as is familiarity with low-power design techniques and scripting in Python, Tcl, or Perl

Who You Are

You can look at a 10,000-line RTL module and spot the structural issue that is going to cause a synthesis problem three steps downstream
You do not wait for perfect specs. You read what is available, flag the gaps, and start building while the architecture team fills in the details
When a CDC violation shows up in a report, you can quickly determine whether it is a real cross-domain hazard or a false positive from an overly conservative tool setting
You communicate clearly with people who do not speak RTL. You can explain a clock domain crossing issue to a verification engineer or a constraint tradeoff to a physical design lead without losing the technical thread
You take ownership. If a block is yours, you see it through lint, CDC, synthesis, and handoff, and you do not consider it done until the next team can actually use it
You are comfortable mentoring others, not because you have all the answers, but because you know how to help someone work through a problem without just giving them the solution

The Team You'll Be Part Of

Your recruiter will

Apply Now

Refine Your Search

r&d engineer jobs in orissa

R&D Engineering, Staff Engineer

Embedded R&D Engineer

Electronics R&D engineer

Embedded R&D Engineer

Production Manager- Advance Material manufacturing/ FPR- Indian Railways

Chief Technology Officer (CTO) & Co-Founder

Embedded R&D Engineer INTERN

Lead Production Manager

Plant Head (Solvent Extraction)

Program Manager - Operations, Odisha

Principal AI Forward Deployment Engineer

Staff DFT Engineer

Production Line Manager - Basic Brick

Production Line Manager - Tap Hole Clay

Sales Representative I - Surgical Innovation

Sales Representative II- Surgical Innovation

Sektionschef Assignment Saab Dynamics

I want to receive the latest job alerts for r&d engineer in orissa

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Category Engineering Hire Type Employee Job ID 17520 Remote Eligible No Date Posted 06/29/2026

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