Kukatpally Hyderabad Telangana Design verification engineer Jobs – 418 Open Jobs Today

CPU Design Verification Engineer
SiFive —Hyderabad, Telangana
- Full-time
- Engineering
- Master's degree
- Bachelor's degree
Engineer / Staff / Sr. Staff Engineer - CPU Verification (RAS)
SiFive —Hyderabad, Telangana
- Full-time
- Master's degree
- Electrical experience
- Bachelor's degree
VHDL Design Engineer
Puneriyas Entertainment —Jubilee Hills, Hyderabad, Telangana
- ₹10,00,000 - ₹12,00,000 a year
- Full-time
- System design
- In-person
- Python
- Health insurance
- Life insurance
Quick apply
Design Verification Engineer (MCU Verification)
Teizosoft Talent acquisition —Hyderabad, Telangana
- Up to ₹20,00,000 a year
- Full-time
- System design
- In-person
- Python
Quick apply
15h
[India] Design Verification Engineer
EdgeCortix —Hyderabad, Telangana
- Full-time
- Hybrid work
- Research
- Scripting
- Communication skills
Quick apply
ASIC Design Verification Engineer
Ceremorphic Technologies —Hyderabad, Telangana
- ₹1 a year
- Full-time
- Scripting
- Python
Quick apply
Design verification engineer
Team Computers —Hyderabad, Telangana
- Full-time
Physical Design Engineer
Corp Match Private Limited —Hyderabad, Telangana
- ₹11,408.18 - ₹45,801.45 a month
- Full-time
- Master's degree
- Bachelor's degree
- Scripting
Quick apply
11d
Design Verification Engineer
Ambit Semiconductors —Hyderabad, Telangana
- Master's degree
- Bachelor's degree
- Mentoring
DFX RTL Design Engineer
Advanced Micro Devices, Inc —Hyderabad, Telangana
- Master's degree
- Analysis skills
- C++
Design Verification (DV) Engineers
Purplenow —Hyderabad, Telangana
- Up to ₹15,00,000 a year
- Full-time
- Scripting
- In-person
- Python
- Health insurance
- Paid time off
Quick apply
10d
Staff Design Verification Engineer
SiFive —Hyderabad, Telangana
- Full-time
- Doctoral degree
- PMP
- B.Sc
2d
Peripherals Design Verification Staff Engineer
Qualcomm —Hyderabad, Telangana
- Doctoral degree
- Computer Science
- Master's degree
10d
RF Design Engineer (3-6yrs)
constelli signals —Hyderabad, Telangana
- ₹7,50,000 - ₹25,00,000 a year
- Weekend availability
- Doctoral degree
- English
- Master's degree
Quick apply
FPGA Design Verification and validation Engineer
Advanced Micro Devices, Inc —Hyderabad, Telangana
- Remote
- B.Sc
- Master's degree
- Bachelor's degree
1d
Low Power Design Engineer (RTL)
Advanced Micro Devices, Inc —Hyderabad, Telangana
- Master's degree
- Analysis skills
- Bachelor's degree
Lead Design Verification Engineer
Advanced Micro Devices, Inc —Hyderabad, Telangana
- Master's degree
- Analysis skills
- Bachelor's degree
Design Verification Engineer
Mirafra Software Technologies —Hyderabad, Telangana
- C++
- Bachelor's degree
- Communication skills
Hardware PCB Design Engineer
Unistring Tech Solutions Pvt. Ltd. —Hyderabad, Telangana
- ₹4,00,000 - ₹10,00,000 a year
- Full-time
- Master's degree
- Electrical experience
- Bachelor's degree
- Health insurance
Quick apply
4d
ASIC Verification Engineer
NVIDIA —Hyderabad, Telangana
- Full-time
- Computer Science
- B.Sc
- Master's degree

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CPU Design Verification Engineer

SiFive -
Hyderabad, Telangana

Apply Now

Job details

Full-time

Qualifications

Buffer (application)
Engineering
Master's degree
Verilog
Bachelor's degree
Machine learning
SystemVerilog

Full job description

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.

Are you ready?

To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.

Job Description:

As part of complex out‑of‑order (OOO) CPU cores verification, we are looking for the role, where you will own verification strategy, methodology, and execution for major core blocks, drive coverage and sign‑off, and act as a technical leader and mentor within the DV team.

Key Responsibilities

Education & Experience:

5+ Years of experience with Bachelor's or Master's in Engineering

Technical Ownership

Own DV for major OOO core subsystems such as:
- Front‑end: fetch, branch prediction, instruction decode.
- Rename / register mapping and dependency tracking.
- Issue queues / schedulers, execution units, bypass networks.
- Reorder buffer (ROB), retirement, exceptions, interrupts, and pipeline flush/replay.
- Load‑store unit (LSU), store buffer, atomics/LR‑SC, fences, speculative loads/stores.
- L1 caches, TLBs, MMU interfaces, and coherence/protocol interfaces.
Translate ISA + micro‑architecture specifications into detailed verification plans and test strategies.

Testbench & Methodology Leadership

Architect and implement System Verilog/UVM testbenches for OOO cores and subsystems:
- Reusable UVM environments, agents, monitors, scoreboards, reference models.
- Constrained‑random and targeted stimulus for OOO corner cases (deep speculation, hazard patterns, reorder stress).
Define and evolve DV methodology for OOO verification:
- Scenario libraries for speculation, memory ordering, and multi‑core interactions.
- Reuse patterns across IPs and projects; contribute to common DV infrastructure.

Coverage, Assertions, and Sign‑off

Define coverage models and sign‑off criteria:
- Functional, code, assertion, and scenario coverage for OOO execution and memory model compliance.
Develop and maintain assertion sets (SVA) for key OOO properties, such as:
- No deadlock/livelock in ROB / scheduler / LSQ.
- Correct branch mispredict, exception, and interrupt recovery.
- Correct load‑store ordering, forwarding, and replay behavior.
Drive coverage closure and sign‑off for owned blocks; review and sign off plans/coverage for peer areas when needed.

Debug & Cross‑Functional Collaboration

Lead debug of complex failures:
- Subtle OOO bugs (hazards, wrong‑path effects, starvation, corner replay conditions).
- Memory ordering and coherence violations across cores and caches.
- TLB/MMU and privilege/protection corner cases.
Work closely with:
- Micro‑architecture and RTL teams to refine designs for correctness and verifiability.
- Performance/modeling teams to align micro‑arch behavior with models and performance targets.
- Post‑silicon teams to reproduce and root‑cause silicon issues in pre‑silicon DV.

Mentoring & Influence

Mentor junior and mid‑level DV engineers in:
- OOO micro‑architecture concepts and debug.
- Testbench design, stimulus generation, coverage, and methodology.
Provide technical leadership across projects:
- Lead DV design and reviews, contribute to architecture/micro‑architecture reviews from a verification perspective.
- Champion best practices in DV and help set technical direction for core verification.

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in:

India

Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.

Apply Now

Refine Your Search

design verification engineer jobs in kukatpally hyderabad telangana

CPU Design Verification Engineer

Engineer / Staff / Sr. Staff Engineer - CPU Verification (RAS)

VHDL Design Engineer

Design Verification Engineer (MCU Verification)

[India] Design Verification Engineer

ASIC Design Verification Engineer

Design verification engineer

Physical Design Engineer

Design Verification Engineer

DFX RTL Design Engineer

Design Verification (DV) Engineers

Staff Design Verification Engineer

Peripherals Design Verification Staff Engineer

RF Design Engineer (3-6yrs)

FPGA Design Verification and validation Engineer

Low Power Design Engineer (RTL)

Lead Design Verification Engineer

Design Verification Engineer

Hardware PCB Design Engineer

ASIC Verification Engineer

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