<h1><b>Job Details:</b></h1><p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Job Description: </h2>We're looking for a hands-on SoC Design Verification Engineer to drive verification for complex SoC/IP blocks. You will own verification planning, UVM testbench development, test content creation (directed and constrained-random), coverage closure, and debug across block, subsystem, and SoC levels. You'll collaborate closely with design, architecture, firmware, and validation teams to deliver high-quality silicon on schedule. What You'll Do (Key Responsibilities) • Own the verification lifecycle for one or more IPs/subsystems/SoC top-level features: requirements decomposition, test plan definition, coverage strategy, execution, and signoff. • Architect and implement UVM environments (agents, drivers, monitors, sequencers, scoreboards, reference models), with scalable, reusable components. • Develop test content: constrained-random sequences, scenario tests, stimulus libraries, checkers, and assertions. • Debug failures quickly and methodically across simulation and emulation (waveforms, logs, assertions, checkers, reference model mismatches). • Drive coverage closure (functional and code coverage): define, measure, analyze holes, and implement closure strategies. • Leverage assertions (SVA) and formal where appropriate to strengthen verification quality and accelerate bug find. • Integrate VIPs (e.g., AXI/ACE/PCIe/DDR) and coordinate with external/internal IP teams for models, checkers, and coverage. • Collaborate cross-functionally with RTL design, architecture, DV, DFT, performance, firmware, and post-silicon validation to ensure feature completeness and testability. • Continuously improve flows: contribute to methodology, regressions, CI/CD, and verification infrastructure (e.g., Makefiles, Python utilities, farm scripts). • Document plans, environments, and results; present status, risks, and signoff evidence to stakeholders.<p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2><b>Qualifications:</b></h2><p>Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.<br /><br />Minimun Qualification<br />• BS/MS in Electrical/Computer Engineering or related field (or equivalent practical experience).<br />• 5+ years of SoC/IP design verification experience<br />• Strong UVM/SystemVerilog development expertise (testbenches, agents, scoreboards, virtual sequences, factory/objection/callback mechanisms).<br />• Test planning experience: translating architectural/RTL specs into measurable, coverage-driven verification plans.<br />• Proven debug skills in simulation/emulation (e.g., Synopsys VCS, Cadence Xcelium, Siemens Questa; waveform tools like Verdi/DVE/SimVision).<br />• Coverage-driven verification: functional coverage modeling, code coverage analysis, coverage closure workflows.<br />• Scripting proficiency (Python, Perl, Shell, Make/CMake) for automation, regressions, and data analysis.<br />• Excellent communication and collaboration; ability to deliver in fast-paced, multi-site environments.<br /><br />Preferred Qualifications:<br />• SoC-level verification experience: fabric/interconnect, security,<br />• Experience with standard protocols: AXI/ACE/CHI, PCIe, LP/DDR, USB, MIPI, I3C, SPI/I2C, Ethernet; integrating and customizing VIP.<br />• Assertion-based verification (SVA) and formal (JasperGold/VC Formal/PropCheck) for property checking and bug hunting.<br />• Power-aware verification (UPF/CPF), isolation/retention, multi-voltage domains.<br />• Emulation/FPGA prototyping (Palladium, Zebu, Veloce), transaction-level acceleration, hybrid verification.<br />• Performance/latency/throughput test content and checkers; scoreboard/reference model design for complex data paths.<br />• Exposure to C/C++/SystemC reference models or firmware-aware verification.<br />• Experience leading small teams, mentoring, or driving signoff for a tapeout.<br /><br />Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.</p><p></p><p> </p><p></p><p></p><h2>Job Type:</h2>Experienced Hire<p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Shift:</h2>Shift 1 (India)<p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Primary Location: </h2>India, Bangalore<p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Additional Locations:</h2><p style="text-align:inherit"></p><p style="text-align:inherit"></p><p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Business group:</h2>Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society.<p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Posting Statement:</h2>All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.<h2></h2><h2>Position of Trust</h2>N/A<p style="text-align:inherit"></p><p style="text-align:left"><b>Work Model for this Role</b></p>This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.<p></p><p>*</p><p></p>ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
