Somajiguda Hyderabad Telangana Junior architect Jobs – 47 Open Jobs Today

ASIC Digital Design, Staff Engineer
Synopsys —Hyderabad, Telangana
- Walk-in
- Master's degree
- Analysis skills
- Bachelor's degree
- Health insurance
15h
Junior Architect
KAYNE BIO SCIENCES LIMITED —Hyderabad, Telangana
- Full-time
- AutoCAD
- Project management
- Bachelor's degree
Quick apply
ASIC Physical Design, Staff Engineer
Synopsys —Hyderabad, Telangana
- Walk-in
- Health insurance
Interior Designer
TechSavis —Hyderabad, Telangana
- ₹11,915.19 - ₹65,600.29 a month
- Full-time
- AutoCAD
- Hospitality
- Microsoft Office
- Commuter assistance
- Health insurance
Quick apply
Jr.Architect
Designer Web —Hyderabad, Telangana
- Email
- Bachelor's degree
Architect
The truth branding —Hyderabad, Telangana
- Full-time
- AutoCAD
- Microsoft Office
- Bachelor's degree
Quick apply
Staff Engineer - Physical Design
Synopsys —Hyderabad, Telangana
- Walk-in
- In-person
- Health insurance
Assistant Project Manager
JLL —Hyderabad, Telangana
- Microsoft Powerpoint
- Microsoft Word
- AutoCAD
- Health insurance
5d
Senior Architect
Lax Air Group Private Limited —Hyderabad, Telangana
- ₹45,000 - ₹60,000 a month
- Full-time
- AutoCAD
- Master's degree
- Bachelor's degree
- Health insurance
- Cell phone reimbursement
Quick apply
1d
Voxela Space Factory
Voxela Space Factory —Hyderabad, Telangana
- From ₹30,000 a month
- Full-time
- AutoCAD
- Presentation skills
- Bachelor's degree
- Commuter assistance
- Paid time off
Quick apply
R&D Engineering, Sr Staff Engineer
Synopsys —Hyderabad, Telangana
- Master's degree
- C++
- Electrical experience
- Health insurance
11d
Senior Civil Engineer
SRI APOORVA CMC LLP —Kollur, Telangana
- ₹30,000 - ₹60,000 a month
- Full-time
- AutoCAD
- Civil engineering
- Microsoft Office
Quick apply
Senior Architect
Prajay Engineers Syndicate Limited —Hyderabad, Telangana
- ₹25,000 - ₹50,000 a month
- Email
- AutoCAD
- Master's degree
- Bachelor's degree
- Flexible schedule
Quick apply
Junior Architects
Heartfulness Education Trust —Shamshabad, Hyderabad, Telangana
- Full-time
- AutoCAD
- Bachelor's degree
- In-person
Quick apply
Junior Architect
Heartfulness Education Trust —Shamshabad, Hyderabad, Telangana
- Full-time
- AutoCAD
- Bachelor's degree
- In-person
Quick apply
SRAM Circuit Design/ Memory Compiler Design Engineer
Advanced Micro Devices, Inc —Hyderabad, Telangana
- Master's degree
- Analysis skills
- Bachelor's degree
Sr Staff Engineer - Analog Design
Synopsys —Hyderabad, Telangana
- B.Sc
- Master's degree
- Electrical experience
- Health insurance
Senior Architect
Heartfulness Education Trust —Shamshabad, Hyderabad, Telangana
- Full-time
- AutoCAD
- Microsoft Office
- Master's degree
Quick apply
CPU Design Verification Engineer
SiFive —Hyderabad, Telangana
- Full-time
- Engineering
- Master's degree
- Bachelor's degree
Senior Architects
Heartfulness Education Trust —Shamshabad, Hyderabad, Telangana
- Full-time
- AutoCAD
- Master's degree
- Presentation skills
Quick apply

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ASIC Digital Design, Staff Engineer

Synopsys -
Hyderabad, Telangana

Apply Now

Job details

15 hours ago

Benefits

Health insurance

Qualifications

Cloud infrastructure
FPGA
Electronics Engineering
Master's degree
Analysis skills
Bachelor's degree
Embedded software
SystemVerilog
Electrical Engineering
AI
Leadership
Debugging

Full job description

We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You are an engineer who gets energized when you see a complex Subsystem come together and actually work, not just pass a basic smoke test, actually work under corner cases that would make most people walk away. You have spent enough time in verification to know that the difference between a clean tapeout and a costly respin often lives in a test case no one thought to write or a coverage hole no one noticed until it was too late. That keeps you up at night in the best way.

You think in test plans, not checklists. When someone hands you a spec for a DDR or PCIe or UCIe interface, you are already mapping out where the edge cases hide and what kind of stimulus will actually stress the design. Debugging a waveform with thousands of signals does not intimidate you, it is where you do your best work. You ask the right questions early, whether that is clarifying an ambiguous requirement with an architect or pushing back on an RTL designer when something does not smell right.

Leading a team does not mean having all the answers. It means knowing when to dive deep yourself and when to unblock someone else. You have mentored engineers before, or you are ready to, and you understand that the best verification environments are built by people who share what they learn. At Synopsys, you will work on Subsystems that power the chips behind AI, automotive, and cloud infrastructure, and the verification rigor you bring will directly determine whether those chips work.

What You'll Be Doing

Lead verification ownership for critical Subsystem areas, driving strategy and execution alongside a team of verification engineers working on DDR, HBM, PCIe, UCIe, Ethernet, UALink, or UFS IP integration
Define, implement, and track detailed verification test plans that map coverage goals to real silicon risk, ensuring nothing slips through
Build and maintain Subsystem-level UVM testbenches in SystemVerilog, integrating RTL and behavioral models into a cohesive verification environment
Write complex test cases, assertions, and checkers that catch the corner cases other teams miss, and debug simulation failures down to root cause
Extract, analyze, and drive closure on functional coverage and code coverage metrics, working with the team to close gaps before signoff
Manage regression suites and contribute to continuous improvement of verification flows, methodologies, and automation
Collaborate directly with RTL designers and architects across global sites to ensure functional correctness and alignment on design intent

The Impact You Will Have

Enable successful verification and deployment of high-performance Subsystems that ship in leading-edge SoCs powering AI, automotive, cloud, and mobile applications worldwide
Catch critical design issues early in the verification cycle, reducing time-to-market and avoiding costly silicon respins that can delay product launches by months
Advance verification methodologies and AI-assisted verification flows that influence how Synopsys and the broader industry approach Subsystem-level verification
Build verification environments and test strategies that become reusable assets across multiple product generations and IP families
Mentor and grow verification engineers on your team, raising the technical bar and building a culture of rigor and knowledge sharing
Strengthen Synopsys' reputation as the premier provider of high-speed connectivity IP Subsystems through engineering excellence that customers depend on
Set industry standards for IP verification quality and methodology, contributing to Synopsys' leadership in chip design and EDA

What You'll Need

Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or a related technical field
8+ years of hands-on experience in ASIC or FPGA verification, with a track record of owning verification deliverables from planning through signoff
Proven expertise developing SystemVerilog and UVM-based testbenches for complex ASIC designs, including experience with assertions, checkers, and constrained random stimulus
Strong ability to define verification strategies, write rigorous test plans, and drive coverage closure using functional coverage and code coverage analysis
Experience technically leading a verification team or mentoring engineers, with demonstrated success collaborating across design, architecture, and verification teams
Deep understanding of verification metrics, regression management, and debugging complex simulation failures in large-scale environments
Experience with high-speed interface protocols such as DDR, HBM, PCIe, UCIe, Ethernet, UALink, or UFS is highly desirable and will set you apart

Who You Are

You can look at a failing regression, pull up the waveform, and within an hour tell the team whether it is a testbench bug, an RTL issue, or a timing corner no one considered
When a junior engineer brings you a stuck debug, you do not just give them the answer, you walk them through how to isolate the problem so they can solve the next one themselves
You push back when a test plan is too shallow or a coverage model misses an important state transition, and you do it in a way that makes the team stronger, not defensive
You stay current on verification techniques and tools, whether that is exploring AI-assisted verification flows or adopting new UVM patterns that improve reuse and debug speed
You communicate clearly across time zones and disciplines, translating verification status into terms that architects, designers, and project leads can act on
You take ownership seriously, if a coverage hole or test gap exists in your area, you do not wait for someone else to notice, you flag it and drive it to closure

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Apply Now

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junior architect jobs in somajiguda hyderabad telangana

ASIC Digital Design, Staff Engineer

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Senior Architects

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