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Analog Design, Staff Engineer

Synopsys -
Bengaluru, Karnataka

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Job details

9 days ago

Qualifications

Scripting
Manufacturing
Python
Shell Scripting

Full job description

Date posted 06/01/2026

Category Engineering Hire Type Employee Job ID 17566 Remote Eligible No Date Posted 06/01/2026

We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years deep in the physics of silicon, designing circuits that live at the boundary between analog behavior and digital logic. You know that a flip flop is not just a schematic, it is a careful negotiation between setup time, hold time, leakage, and clock load, and you have learned to make those tradeoffs without losing sleep or performance. The difference between a cell that works in simulation and one that works in production across voltage corners, temperature swings, and process variation is something you have debugged enough times to see coming three steps ahead.

You are comfortable moving between SPICE simulations, post-layout extraction flows, and Python scripting to automate the parts that should not require manual intervention. Latch-up rules, electromigration limits, and design rule decks are not obstacles, they are constraints you design within, and you know how to push back when a spec does not make sense. You care about PPA because you have seen what happens when power or area gets ignored until tapeout, and you would rather catch it now. At Synopsys, you will work on standard cells that go into libraries used across the industry, and the circuits you design will matter at scale.

What You'll Be Doing

Design and develop high-performance standard cells including flip flops, latches, multibit flip flops, voltage level shifters, power switches, clock buffers, and complex sequential logic
Build and refine post-layout extraction environments to validate circuit performance against parasitic effects and real-world operating conditions
Optimize digital and analog circuit topologies for power, performance, and area across multiple process nodes and operating corners
Perform statistical and variation analysis using Monte Carlo and corner-based methods to ensure robustness across manufacturing spread
deep knowledge of CMOS device physics, design rules, latch-up prevention, and electromigration constraints to ensure reliable, manufacturable designs
Collaborate with layout teams to close timing, power, and area targets while maintaining design intent through the physical implementation flow
Automate repetitive design and analysis tasks using Python, shell scripting, or ICV to improve team efficiency and design consistency

The Impact You Will Have

Your standard cell designs will be integrated into Synopsys IP libraries used by customers building chips for AI, automotive, mobile, and high-performance computing applications
Improvements you make in flip flop performance or leakage will directly influence the power and speed of chips designed by leading semiconductor companies worldwide
Your work on power optimization cells and level shifters will enable more energy-efficient SoCs, contributing to longer battery life and lower operating costs
The robustness and variation tolerance you build into your designs will reduce yield loss and improve manufacturing success rates for our customers
Collaboration across design, layout, and characterization teams will accelerate library development cycles and improve time-to-market for new process nodes
Your contributions to automation and methodology will raise the quality bar for the entire standard cell design team

What You'll Need

5 to 8 years of hands-on experience in standard cell circuit design, with a focus on high-performance flip flops, latches, multibit flip flops, voltage level shifters, power cells, and clock cells
Strong understanding of CMOS device characteristics, design rules, latch-up mechanisms, and electromigration constraints
Proven experience developing post-layout extraction environments and validating circuit performance with parasitic-aware simulations
Solid background in digital circuit design and optimization techniques targeting better power, performance, and area tradeoffs
Hands-on experience with statistical and variation analysis methods to assess circuit robustness across process, voltage, and temperature corners
Familiarity with Python, shell scripting, or ICV for design automation is a strong plus
Knowledge of standard cell layout principles and physical design considerations is a plus

Who You Are

You can look at a post-layout netlist and immediately spot the parasitic that is killing your setup margin, and you know which knob to turn to fix it without breaking something else
You are comfortable sitting with a layout engineer to debug a DRC violation or an unexpected coupling cap, and you can explain why it matters without sounding condescending
You do not treat corner files as black boxes, you understand what SS, FF, and FS actually mean for your transistor stack, and you design accordingly
You push back when a specification is unrealistic or incomplete, and you do it with data, not opinion
You are organized enough to track multiple cell designs through different stages of verification, characterization, and signoff without losing threads or missing deadlines
You communicate clearly in writing and in conversation, whether you are documenting a design decision or explaining a timing failure to a cross-functional team

The Team You'll Be Part Of

Your recruiter will

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