Chief engineer Jobs

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Quick apply
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16h

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Lead RTL Design Engineer

Larsen & Toubro -
Bengaluru, Karnataka

Apply Now

Job details

Qualifications

Computer Science
BSEE
Verilog
C++
SoC
Electrical experience
C
Bachelor's degree
Embedded software
Perl
Scripting
SystemVerilog
Electrical Engineering
Communication skills
Python
Debugging

Full job description

Lead RTL Design Engineer

LNT/LRDE/1553275

LTST-L&T Semiconductor Technologies Limited
Bengaluru

Posted On 29 Dec 2025
End Date 27 Jun 2026
Required Experience 12 - 17 years

Skills

Knowledge & Posting Location

RTL design RTL Development RTL coding Verilog LINT CDC

Minimum Qualification

Bachelor Of Electrical Engineering (BEE)

Job Description

Purpose:

LTSCT’s Chief Development Organization and Global Engineering team is a central engineering organization responsible for developing and delivering Systems-on-a-Chip (SoCs) for LTSCT's Automotive, Industrial, Energy and Telecom infra business lines. The team is challenged to produce industry-leading solutions covering very cost-sensitive, low power devices to highly integrated, high performance, multi-domain devices compliant with the latest automotive and industrial safety and security standards.

Areas of Responsibilities:

Contribute to the RTL delivery for a multitude of projects.
Work closely with system architects to define high level specifications that are implementable and robust, and Interface with verification/validation teams to ensure design quality and robustness.
Build strong collaboration with other R&D teams such as Verification, digital IP, Design Enablement, Emulation, and Validation to achieve project milestones.
Promote continuous improvement to design techniques to ensure ‘Zero Defect’ chips.
Collaborate with SME’s and key leaders in architecture, systems, emulation, SoC design, software, physical design, and IP teams developing key technical networks to influence.

Qualifications:

At least 5+years of experience in related domains and have working knowledge.
Degree in Electrical Engineering or Computer Science, with 7+ years of experience on IP/Sub-System RTL Design.
Experience in testbench design and development using UVM methodology for IP/Subsystem and SOC.
Experience in Microcontroller and Microprocessor architecture, Interconnect, Cache Coherency.
Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR/DDR3/4) and memory controllers.
Experience and knowledge of Verilog, System Verilog, C/C++, Shell.
Good knowledge in scripting like Perl, TCL or Python is a plus.
Proficiency in Metric Driven Verification concepts, functional and code coverage.
Expertise in directed and constrained random methodologies.
Good knowledge of formal verification methodologies and assertions.
Experience with debugging of designs pre- and post-silicon, in simulation and on the bench.
Excellent written and verbal communication skills.
Experience with System Verilog and front-end tooling (simulation, waveform viewers, lint, CDC, RDC, etc.) is required, as well as highly efficient FE methodologies.
Strong domain knowledge of clocking, system modes, power management, debug, security and other architectures is a must.
Any of following experience would be a plus: High Speed Peripherals like DDR, PCIe, Ethernet, GPU, VPU (Video Processing Unit); NIC/FlexNOC interconnect; Flash memory subsystems

Apply Now

Refine Your Search

Lead RTL Design Engineer

Electrical Technician

A/C Technician

HVAC Technician

Chief Engineer

Chief Engineer

Chief Engineer for Self -Unloader – end April (Hiring Office: India)

Fourth Engineer

Chief Engineer for Bulk Carrier – end March (Hiring Office: India)

Cheif Engineer

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Third Engineer

Chief Engineer for LNG Carrier – beg June (Hiring Office: India)

Chief Engineer for Chemical Tanker – beg May (Hiring Office: India)

Electrical Officer

Second Engineer

NK-69: Site Engineer (E & M)/ Depot, Surat

Electrical officer Prithampur

Sr Engineer - Instrumentation & Controls

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Lead RTL Design Engineer

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